Datasheet

TLV320AIC3104
www.ti.com SLAS510C –FEBRUARY 2007–REVISED DECEMBER 2010
Table 28. Page 0/Register 53: PGA_L to HPLCOM Volume Control Register
BIT READ/ RESET DESCRIPTION
WRITE VALUE
D7 R/W 0 PGA_L Output Routing Control
0: PGA_L is not routed to HPLCOM.
1: PGA_L is routed to HPLCOM.
D6–D0 R/W 000 0000 PGA_L to HPLCOM Analog Volume Control
For 7-bit register settings versus analog gain values, see Table 19.
Table 29. Page 0/Register 54: DAC_L1 to HPLCOM Volume Control Register
BIT READ/ RESET DESCRIPTION
WRITE VALUE
D7 R/W 0 DAC_L1 Output Routing Control
0: DAC_L1 is not routed to HPLCOM.
1: DAC_L1 is routed to HPLCOM.
D6–D0 R/W 000 0000 DAC_L1 to HPLCOM Analog Volume Control
For 7-bit register settings versus analog gain values, see Table 19.
Table 30. Page 0/Register 55: Reserved Register
BIT READ/ RESET DESCRIPTION
WRITE VALUE
D7–D0 R/W 0000 0000 Reserved. Do not write to this register.
Table 31. Page 0/Register 56: PGA_R to HPLCOM Volume Control Register
BIT READ/ RESET DESCRIPTION
WRITE VALUE
D7 R/W 0 PGA_R Output Routing Control
0: PGA_R is not routed to HPLCOM.
1: PGA_R is routed to HPLCOM.
D6–D0 R/W 000 0000 PGA_R to HPLCOM Analog Volume Control
For 7-bit register settings versus analog gain values, see Table 19.
Table 32. Page 0/Register 57: DAC_R1 to HPLCOM Volume Control Register
BIT READ/ RESET DESCRIPTION
WRITE VALUE
D7 R/W 0 DAC_R1 Output Routing Control
0: DAC_R1 is not routed to HPLCOM.
1: DAC_R1 is routed to HPLCOM.
D6–D0 R/W 000 0000 DAC_R1 to HPLCOM Analog Volume Control
For 7-bit register settings versus analog gain values, see Table 19.
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