Datasheet

TLV320AIC3104
SLAS510C –FEBRUARY 2007–REVISED DECEMBER 2010 www.ti.com
Page 0/Register 2: Codec Sample Rate Select Register
BIT READ/ RESET DESCRIPTION
WRITE VALUE
D7–D4 R/W 0000 ADC Sample Rate Select
(1)
0000: ADC f
S
= f
S(ref)
/1
0001: ADC f
S
= f
S(ref)
/1.5
0010: ADC f
S
= f
S(ref)
/2
0011: ADC f
S
= f
S(ref)
/2.5
0100: ADC f
S
= f
S(ref)
/3
0101: ADC f
S
= f
S(ref)
/3.5
0110: ADC f
S
= f
S(ref)
/4
0111: ADC f
S
= f
S(ref)
/4.5
1000: ADC f
S
= f
S(ref)
/5
1001: ADC f
S
= f
S(ref)
/5.5
1010: ADC f
S
= f
S(ref)
/6
1011–1111: Reserved. Do not write these sequences.
D3–D0 R/W 0000 DAC Sample Rate Select
(1)
0000: DAC f
S
= f
S(ref)
/1
0001: DAC f
S
= f
S(ref)
/1.5
0010: DAC f
S
= f
S(ref)
/2
0011: DAC f
S
= f
S(ref)
/2.5
0100: DAC f
S
= f
S(ref)
/3
0101: DAC f
S
= f
S(ref)
/3.5
0110: DAC f
S
= f
S(ref)
/4
0111: DAC f
S
= f
S(ref)
/4.5
1000: DAC f
S
= f
S(ref)
/5
1001: DAC f
S
= f
S(ref)
/5.5
1010: DAC f
S
= f
S(ref)
/6
1011–1111 : Reserved, do not write these sequences.
(1) In the TLV320AIC3104, the ADC f
S
must be set equal to the DAC f
S
. This is done by setting the value of bits D7–D4 equal to the value
of bits D3–D0.
Page 0/Register 3: PLL Programming Register A
BIT READ/ RESET DESCRIPTION
WRITE VALUE
D7 R/W 0 PLL Control Bit
0: PLL is disabled.
1: PLL is enabled.
D6–D3 R/W 0010 PLL Q Value
0000: Q = 16
0001: Q = 17
0010: Q = 2
0011: Q = 3
0100: Q = 4
…
1110: Q = 14
1111: Q = 15
D2–D0 R/W 000 PLL P Value
000: P = 8
001: P = 1
010: P = 2
011: P = 3
100: P = 4
101: P = 5
110: P = 6
111: P = 7
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