Datasheet

Audio Serial Bus Interface
I
2
C Serial
Control Bus
Bias/
Reference
MICBIAS
SCL
SDA
RESET
Voltage Supplies
Audio Clock
Generation
MCLK
LINE2L
PGA
0/+59.5dB
0.5dB
Steps
ADC
+
+
+
+ + +
VCM
VCM
DAC
L
+
Volume
Control
Effects
DIN
DOUT
BCLK
WCLK
DINL
DINR
DOUTL
DOUTR
MIC2R/LINE2R
LINE2R
ADC
PGA
0/+59.5dB
0.5dB
Steps
+
DAC
R
Volume
Control
Effects
AGC
AGC
SW-D2
SW-D1
SW-D3
SW-D4
DVDD
DRVDD
DRVDD
DRVSS
DVSS
IOVDD
AVSS1
AVDD
AVSS2
HPROUT HPRCOM HPLCOM HPLOUT
LEFT_LOP
LEFT_LOM
LINE1LP LINE2LP
LINE1LM LINE1RM
SW-L0
SW-L1
SW-L2
SW-L4
SW-L3
SW-R4
SW-R3
RIGHT_LOP
RIGHT_LOM
LINE1RP LINE2RP
SW-R0
SW-R1
SW-R2
B0151-01
MIC1RP/LINE1RP
MIC1RM/LINE1RM
LINE1RP
LINE1RM
MIC1LP/LINE1LP
MIC1LM/LINE1LM
LINE1LP
LINE1LM
MIC2L/LINE2L/
MICDET
TLV320AIC3104
www.ti.com SLAS510C –FEBRUARY 2007–REVISED DECEMBER 2010
SIMPLIFIED BLOCK DIAGRAM
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