Datasheet

DA(6) DA(0) RA(7) RA(0)
SDA
SCL
DA(6) DA(0) D(7) D(0)
(M) – SDA ControlledbyMaster
(S) – SDA ControlledbySlave
Start
(M)
Write
(M)
Slave
Ack
(S)
Slave
Ack
(S)
Slave
Ack
(S)
Master
No Ack
(M)
Stop
(M)
Repeat
Start
(M)
Read
(M)
7-BitDevice Address
(M)
8-BitRegister Address
(M)
8-BitRegisterData
(S)
7-BitDevice Address
(M)
T0148-01
DA(6) DA(0) RA(7) RA(0) D(7) D(0)
T0147-01
SDA
SCL
(M) – SDA ControlledbyMaster
(S) – SDA ControlledbySlave
Start
(M)
Write
(M)
Slave
Ack
(S)
Slave
Ack
(S)
Slave
Ack
(S)
Stop
(M)
7-BitDevice Address
(M)
8-BitRegister Address
(M)
8-BitRegisterdata
(M)
TLV320AIC3104
SLAS510C –FEBRUARY 2007–REVISED DECEMBER 2010 www.ti.com
Most of the time the bus is idle, no communication is taking place, and both lines are HIGH. When
communication is taking place, the bus is active. Only master devices can start a communication. They do this by
causing a START condition on the bus. Normally, the data line is only allowed to change state while the clock
line is LOW. If the data line changes state while the clock line is HIGH, it is either a START condition or its
counterpart, a STOP condition. A START condition is when the clock line is HIGH and the data line goes from
HIGH to LOW. A STOP condition is when the clock line is HIGH and the data line goes from LOW to HIGH.
After the master issues a START condition, it sends a byte that indicates which slave device it wants to
communicate with. This byte is called the address byte. Each device on an I
2
C bus has a unique 7-bit address to
which it responds. (Slaves can also have 10-bit addresses; see the I
2
C specification for details.) The master
sends an address in the address byte, together with a bit that indicates whether it wishes to read from or write to
the slave device.
Every byte transmitted on the I
2
C bus, whether it is address or data, is acknowledged with an acknowledge bit.
When a master has finished sending a byte (eight data bits) to a slave, it stops driving SDA and waits for the
slave to acknowledge the byte. The slave acknowledges the byte by pulling SDA LOW. The master then sends a
clock pulse to clock the acknowledge bit. Similarly, when a master has finished reading a byte, it pulls SDA LOW
to acknowledge this to the slave. It then sends a clock pulse to clock the bit.
A not-acknowledge is performed by simply leaving SDA HIGH during an acknowledge cycle. If a device is not
present on the bus, and the master attempts to address it, it receives a not-acknowledge because no device is
present at that address to pull the line LOW.
When a master has finished communicating with a slave, it may issue a STOP condition. When a STOP
condition is issued, the bus becomes idle again. A master may also issue another START condition. When a
START condition is issued while the bus is active, it is called a repeated START condition.
The TLV320AIC3104 also responds to and acknowledges a general call, which consists of the master issuing a
command with a slave-address byte of 00h.
Figure 16. I
2
C Write
Figure 17. I
2
C Read
In the case of an I
2
C register write, if the master does not issue a STOP condition, then the device enters auto-
increment mode. So in the next eight clocks, the data on SDA is treated as data for the next incremental register.
Similarly, in the case of an I
2
C register read, after the device has sent out the 8-bit data from the addressed
register, if the master issues an acknowledge, the slave takes over control of the SDA bus and transmits for the
next 8 clocks the data of the next incremental register.
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