Datasheet
Table Of Contents
- FEATURES
- APPLICATIONS
- DESCRIPTION
- DESCRIPTION (Continued)
- PIN ASSIGNMENTS
- ABSOLUTE MAXIMUM RATINGS
- PACKAGE THERMAL RATINGS
- SYSTEM THERMAL CHARACTERISTICS
- RECOMMENDED OPERATING CONDITIONS
- ELECTRICAL CHARACTERISTICS
- TYPICAL CHARACTERISTICS
- OVERVIEW
- HARDWARE RESET
- DIGITAL CONTROL SERIAL INTERFACE
- I2C CONTROL INTERFACE
- I2C BUS DEBUG IN A GLITCHED SYSTEM
- DIGITAL AUDIO DATA SERIAL INTERFACE
- RIGHT-JUSTIFIED MODE
- LEFT-JUSTIFIED MODE
- I2S MODE
- DSP MODE
- TDM DATA TRANSFER
- AUDIO DATA CONVERTERS
- AUDIO CLOCK GENERATION
- STEREO AUDIO ADC
- DIGITAL AUDIO PROCESSING FOR RECORD PATH
- AUTOMATIC GAIN CONTROL (AGC)
- STEREO AUDIO DAC
- DIGITAL AUDIO PROCESSING FOR PLAYBACK
- DIGITAL INTERPOLATION FILTER
- DELTA-SIGMA AUDIO DAC
- AUDIO DAC DIGITAL VOLUME CONTROL
- INCREASING DAC DYNAMIC RANGE
- ANALOG OUTPUT COMMON-MODE ADJUSTMENT
- AUDIO DAC POWER CONTROL
- AUDIO ANALOG INPUTS
- ANALOG INPUT BYPASS PATH FUNCTIONALITY
- ADC PGA SIGNAL BYPASS PATH FUNCTIONALITY
- INPUT IMPEDANCE AND VCM CONTROL
- MICBIAS GENERATION
- PASSIVE ANALOG BYPASS DURING POWER DOWN
- ANALOG FULLY DIFFERENTIAL LINE OUTPUT DRIVERS
- ANALOG HIGH-POWER OUTPUT DRIVERS
- SHORT-CIRCUIT OUTPUT PROTECTION
- JACK/HEADSET DETECTION
- CONTROL REGISTERS
- Output Stage Volume Controls
TLV320AIC3101
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........................................................................................................................................ SLAS520D – FEBRUARY 2007 – REVISED DECEMBER 2008
Page 0/Register 101: Clock Register
BIT READ/ RESET DESCRIPTION
WRITE VALUE
D7 – D1 R 0000 000 Reserved. Write only zeros to these bits.
D0 R/W 0 CODEC_CLKIN Source Selection
0: CODEC_CLKIN uses PLLDIV_OUT
1: CODEC_CLKIN uses CLKDIV_OUT
Page 0/Register 102: Clock Generation Control Register
BIT READ/ RESET DESCRIPTION
WRITE VALUE
D7 – D6 R/W 00 CLKDIV_IN Source Selection
00: CLKDIV_IN uses MCLK
01: CLKDIV_IN uses GPIO2
10: CLKDIV_IN uses BCLK
11: Reserved. Do not use.
D5 – D4 R/W 00 PLLCLK_IN Source Selection
00: PLLCLK_IN uses MCLK
01: PLLCLK_IN uses GPIO2
10: PLLCLK _IN uses BCLK
11: Reserved. Do not use.
D3 – D0 R/W 0010 Reserved. Write only 0010 to these bits.
Page 0/Register 103: Left-AGC New Programmable Attack Time Register
BIT READ/ RESET DESCRIPTION
WRITE VALUE
D7 R/W 0 Attack Time Register Selection
0: Attack time for the left AGC is generated from page 0, register 26.
1: Attack time for the left AGC is generated from this register.
D6 – D5 R/W 00 Baseline AGC Attack time
00: Left-AGC attack time = 7 ms
01: Left-AGC attack time = 8 ms
10: Left-AGC attack time = 10 ms
11: Left-AGC attack time = 11 ms
D4 – D2 R/W 000 Multiplication Factor for Baseline AGC
000: Multiplication factor for the baseline AGC attack time = 1
001: Multiplication factor for the baseline AGC attack time = 2
010: Multiplication factor for the baseline AGC attack time = 4
011: Multiplication factor for the baseline AGC attack time = 8
100: Multiplication factor for the baseline AGC attack time = 16
101: Multiplication factor for the baseline AGC attack time = 32
110: Multiplication factor for the baseline AGC attack time = 64
111: Multiplication factor for the baseline AGC attack time = 128
D1 – D0 R/W 00 Reserved. Write only zeros to these bits.
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