Datasheet
Table Of Contents
- FEATURES
- APPLICATIONS
- DESCRIPTION
- DESCRIPTION (Continued)
- PIN ASSIGNMENTS
- ABSOLUTE MAXIMUM RATINGS
- PACKAGE THERMAL RATINGS
- SYSTEM THERMAL CHARACTERISTICS
- RECOMMENDED OPERATING CONDITIONS
- ELECTRICAL CHARACTERISTICS
- TYPICAL CHARACTERISTICS
- OVERVIEW
- HARDWARE RESET
- DIGITAL CONTROL SERIAL INTERFACE
- I2C CONTROL INTERFACE
- I2C BUS DEBUG IN A GLITCHED SYSTEM
- DIGITAL AUDIO DATA SERIAL INTERFACE
- RIGHT-JUSTIFIED MODE
- LEFT-JUSTIFIED MODE
- I2S MODE
- DSP MODE
- TDM DATA TRANSFER
- AUDIO DATA CONVERTERS
- AUDIO CLOCK GENERATION
- STEREO AUDIO ADC
- DIGITAL AUDIO PROCESSING FOR RECORD PATH
- AUTOMATIC GAIN CONTROL (AGC)
- STEREO AUDIO DAC
- DIGITAL AUDIO PROCESSING FOR PLAYBACK
- DIGITAL INTERPOLATION FILTER
- DELTA-SIGMA AUDIO DAC
- AUDIO DAC DIGITAL VOLUME CONTROL
- INCREASING DAC DYNAMIC RANGE
- ANALOG OUTPUT COMMON-MODE ADJUSTMENT
- AUDIO DAC POWER CONTROL
- AUDIO ANALOG INPUTS
- ANALOG INPUT BYPASS PATH FUNCTIONALITY
- ADC PGA SIGNAL BYPASS PATH FUNCTIONALITY
- INPUT IMPEDANCE AND VCM CONTROL
- MICBIAS GENERATION
- PASSIVE ANALOG BYPASS DURING POWER DOWN
- ANALOG FULLY DIFFERENTIAL LINE OUTPUT DRIVERS
- ANALOG HIGH-POWER OUTPUT DRIVERS
- SHORT-CIRCUIT OUTPUT PROTECTION
- JACK/HEADSET DETECTION
- CONTROL REGISTERS
- Output Stage Volume Controls
TLV320AIC3101
www.ti.com
........................................................................................................................................ SLAS520D – FEBRUARY 2007 – REVISED DECEMBER 2008
Page 0/Register 86: LEFT_LOP/M Output Level Control Register
BIT READ/ RESET DESCRIPTION
WRITE VALUE
D7 – D4 R/W 0000 LEFT_LOP/M Output Level Control
0000: Output level control = 0 dB
0001: Output level control = 1 dB
0010: Output level control = 2 dB
...
1000: Output level control = 8 dB
1001: Output level control = 9 dB
1010 – 1111: Reserved. Do not write these sequences.
D3 R/W 0 LEFT_LOP/M Mute
0: LEFT_LOP/M is muted.
1: LEFT_LOP/M is not muted.
D2 R 0 Reserved. Do not write to this register bit.
D1 R 1 LEFT_LOP/M Volume Control Status
0: All programmed gains to LEFT_LOP/M have been applied.
1: Not all programmed gains to LEFT_LOP/M have been applied yet.
D0 R 0 LEFT_LOP/M Power Status
0: LEFT_LOP/M is not fully powered up.
1: LEFT_LOP/M is fully powered up.
Page 0/Register 87: Reserved Register
BIT READ/ RESET DESCRIPTION
WRITE VALUE
D7 – D0 R/W 0000 0000 Reserved. Do not write to this register.
Page 0/Register 88: PGA_L to RIGHT_LOP/M Volume Control Register
BIT READ/ RESET DESCRIPTION
WRITE VALUE
D7 R/W 0 PGA_L Output Routing Control
0: PGA_L is not routed to RIGHT_LOP/M.
1: PGA_L is routed to RIGHT_LOP/M.
D6 – D0 R/W 000 0000 PGA_L to RIGHT_LOP/M Analog Volume Control
For 7-bit register setting versus analog gain values, see Table 6 .
Page 0/Register 89: DAC_L1 to RIGHT_LOP/M Volume Control Register
BIT READ/ RESET DESCRIPTION
WRITE VALUE
D7 R/W 0 DAC_L1 Output Routing Control
0: DAC_L1 is not routed to RIGHT_LOP/M.
1: DAC_L1 is routed to RIGHT_LOP/M.
D6 – D0 R/W 000 0000 DAC_L1 to RIGHT_LOP/M Analog Volume Control
For 7-bit register setting versus analog gain values, see Table 6 .
Page 0/Register 90: Reserved Register
BIT READ/ RESET DESCRIPTION
WRITE VALUE
D7 – D0 R/W 0000 0000 Reserved. Do not write to this register.
Page 0/Register 91: PGA_R to RIGHT_LOP/M Volume Control Register
BIT READ/ RESET DESCRIPTION
WRITE VALUE
D7 R/W 0 PGA_R Output Routing Control
0: PGA_R is not routed to RIGHT_LOP/M.
1: PGA_R is routed to RIGHT_LOP/M.
D6 – D0 R/W 000 0000 PGA_R to RIGHT_LOP/M Analog Volume Control
For 7-bit register setting versus analog gain values, see Table 6 .
Copyright © 2007 – 2008, Texas Instruments Incorporated Submit Documentation Feedback 71
Product Folder Link(s): TLV320AIC3101