Datasheet
Table Of Contents
- FEATURES
- APPLICATIONS
- DESCRIPTION
- DESCRIPTION (Continued)
- PIN ASSIGNMENTS
- ABSOLUTE MAXIMUM RATINGS
- PACKAGE THERMAL RATINGS
- SYSTEM THERMAL CHARACTERISTICS
- RECOMMENDED OPERATING CONDITIONS
- ELECTRICAL CHARACTERISTICS
- TYPICAL CHARACTERISTICS
- OVERVIEW
- HARDWARE RESET
- DIGITAL CONTROL SERIAL INTERFACE
- I2C CONTROL INTERFACE
- I2C BUS DEBUG IN A GLITCHED SYSTEM
- DIGITAL AUDIO DATA SERIAL INTERFACE
- RIGHT-JUSTIFIED MODE
- LEFT-JUSTIFIED MODE
- I2S MODE
- DSP MODE
- TDM DATA TRANSFER
- AUDIO DATA CONVERTERS
- AUDIO CLOCK GENERATION
- STEREO AUDIO ADC
- DIGITAL AUDIO PROCESSING FOR RECORD PATH
- AUTOMATIC GAIN CONTROL (AGC)
- STEREO AUDIO DAC
- DIGITAL AUDIO PROCESSING FOR PLAYBACK
- DIGITAL INTERPOLATION FILTER
- DELTA-SIGMA AUDIO DAC
- AUDIO DAC DIGITAL VOLUME CONTROL
- INCREASING DAC DYNAMIC RANGE
- ANALOG OUTPUT COMMON-MODE ADJUSTMENT
- AUDIO DAC POWER CONTROL
- AUDIO ANALOG INPUTS
- ANALOG INPUT BYPASS PATH FUNCTIONALITY
- ADC PGA SIGNAL BYPASS PATH FUNCTIONALITY
- INPUT IMPEDANCE AND VCM CONTROL
- MICBIAS GENERATION
- PASSIVE ANALOG BYPASS DURING POWER DOWN
- ANALOG FULLY DIFFERENTIAL LINE OUTPUT DRIVERS
- ANALOG HIGH-POWER OUTPUT DRIVERS
- SHORT-CIRCUIT OUTPUT PROTECTION
- JACK/HEADSET DETECTION
- CONTROL REGISTERS
- Output Stage Volume Controls
TLV320AIC3101
SLAS520D – FEBRUARY 2007 – REVISED DECEMBER 2008 ........................................................................................................................................
www.ti.com
Page 0/Register 34: Left-AGC Noise Gate Debounce Register
BIT READ/ RESET DESCRIPTION
WRITE VALUE
D7 – D3 R/W 0000 0 Left-AGC Noise Detection Debounce Control
These times
(1)
are not accurate when double-rate audio mode is enabled.
0000 0: Debounce = 0 ms
0000 1: Debounce = 0.5 ms
0001 0: Debounce = 1 ms
0001 1: Debounce = 2 ms
0010 0: Debounce = 4 ms
0010 1: Debounce = 8 ms
0011 0: Debounce = 16 ms
0011 1: Debounce = 32 ms
0100 0: Debounce = 64 × 1 = 64 ms
0100 1: Debounce = 64 × 2 = 128 ms
0101 0: Debounce = 64 × 3 = 192 ms
…
1111 0: Debounce = 64 × 23 = 1472 ms
1111 1: Debounce = 64 × 24 = 1536 ms
D2 – D0 R/W 000 Left-AGC Signal Detection Debounce Control
These times
(1)
are not accurate when double-rate audio mode is enabled.
000: Debounce = 0 ms
001: Debounce = 0.5 ms
010: Debounce = 1 ms
011: Debounce = 2 ms
100: Debounce = 4 ms
101: Debounce = 8 ms
110: Debounce = 16 ms
111: Debounce = 32 ms
(1) Time constants are valid when DRA is not enabled. The values change when DRA is enabled.
Page 0/Register 35: Right-AGC Noise Gate Debounce Register
BIT READ/ RESET DESCRIPTION
WRITE VALUE
D7 – D3 R/W 0000 0 Right-AGC Noise Detection Debounce Control
These times
(1)
are not accurate when double-rate audio mode is enabled.
0000 0: Debounce = 0 ms
0000 1: Debounce = 0.5 ms
0001 0: Debounce = 1 ms
0001 1: Debounce = 2 ms
0010 0: Debounce = 4 ms
0010 1: Debounce = 8 ms
0011 0: Debounce = 16 ms
0011 1: Debounce = 32 ms
0100 0: Debounce = 64 × 1 = 64 ms
0100 1: Debounce = 64 × 2 = 128 ms
0101 0: Debounce = 64 × 3 = 192 ms
…
1111 0: Debounce = 64 × 23 = 1472 ms
1111 1: Debounce = 64 × 24 = 1536 ms
D2 – D0 R/W 000 Right-AGC Signal Detection Debounce Control
These times
(1)
are not accurate when double-rate audio mode is enabled.
000: Debounce = 0 ms
001: Debounce = 0.5 ms
010: Debounce = 1 ms
011: Debounce = 2 ms
100: Debounce = 4 ms
101: Debounce = 8 ms
110: Debounce = 16 ms
111: Debounce = 32 ms
(1) Time constants are valid when DRA is not enabled. The values would change when DRA is enabled.
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