Datasheet
Table Of Contents
- FEATURES
- APPLICATIONS
- DESCRIPTION
- DESCRIPTION (Continued)
- PIN ASSIGNMENTS
- ABSOLUTE MAXIMUM RATINGS
- PACKAGE THERMAL RATINGS
- SYSTEM THERMAL CHARACTERISTICS
- RECOMMENDED OPERATING CONDITIONS
- ELECTRICAL CHARACTERISTICS
- TYPICAL CHARACTERISTICS
- OVERVIEW
- HARDWARE RESET
- DIGITAL CONTROL SERIAL INTERFACE
- I2C CONTROL INTERFACE
- I2C BUS DEBUG IN A GLITCHED SYSTEM
- DIGITAL AUDIO DATA SERIAL INTERFACE
- RIGHT-JUSTIFIED MODE
- LEFT-JUSTIFIED MODE
- I2S MODE
- DSP MODE
- TDM DATA TRANSFER
- AUDIO DATA CONVERTERS
- AUDIO CLOCK GENERATION
- STEREO AUDIO ADC
- DIGITAL AUDIO PROCESSING FOR RECORD PATH
- AUTOMATIC GAIN CONTROL (AGC)
- STEREO AUDIO DAC
- DIGITAL AUDIO PROCESSING FOR PLAYBACK
- DIGITAL INTERPOLATION FILTER
- DELTA-SIGMA AUDIO DAC
- AUDIO DAC DIGITAL VOLUME CONTROL
- INCREASING DAC DYNAMIC RANGE
- ANALOG OUTPUT COMMON-MODE ADJUSTMENT
- AUDIO DAC POWER CONTROL
- AUDIO ANALOG INPUTS
- ANALOG INPUT BYPASS PATH FUNCTIONALITY
- ADC PGA SIGNAL BYPASS PATH FUNCTIONALITY
- INPUT IMPEDANCE AND VCM CONTROL
- MICBIAS GENERATION
- PASSIVE ANALOG BYPASS DURING POWER DOWN
- ANALOG FULLY DIFFERENTIAL LINE OUTPUT DRIVERS
- ANALOG HIGH-POWER OUTPUT DRIVERS
- SHORT-CIRCUIT OUTPUT PROTECTION
- JACK/HEADSET DETECTION
- CONTROL REGISTERS
- Output Stage Volume Controls
TLV320AIC3101
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........................................................................................................................................ SLAS520D – FEBRUARY 2007 – REVISED DECEMBER 2008
Page 0/Register 25: MICBIAS Control Register
BIT READ/ RESET DESCRIPTION
WRITE VALUE
D7 – D6 R/W 00 MICBIAS Level Control
00: MICBIAS output is powered down.
01: MICBIAS output is powered to 2 V.
10: MICBIAS output is powered to 2.5 V.
11: MICBIAS output is connected to AVDD
D5 – D3 R 000 Reserved. Write only zeros to these bits.
D2 – D0 R XXX Reserved. Write only zeros to these bits.
Page 0/Register 26: Left-AGC Control Register A
BIT READ/ RESET DESCRIPTION
WRITE VALUE
D7 R/W 0 Left-AGC Enable
0: Left AGC is disabled.
1: Left AGC is enabled.
D6 – D4 R/W 000 Left-AGC Target Level
000: Left-AGC target level = – 5.5 dB
001: Left-AGC target level = – 8 dB
010: Left-AGC target level = – 10 dB
011: Left-AGC target level = – 12 dB
100: Left-AGC target level = – 14 dB
101: Left-AGC target level = – 17 dB
110: Left-AGC target level = – 20 dB
111: Left-AGC target level = – 24 dB
D3 – D2 R/W 00 Left-AGC Attack Time
These time constants
(1)
are not accurate when double-rate audio mode is enabled.
00: Left-AGC attack time = 8 ms
01: Left-AGC attack time = 11 ms
10: Left-AGC attack time = 16 ms
11: Left-AGC attack time = 20 ms
D1 – D0 R/W 00 Left-AGC Decay Time
These time constants
(1)
are not accurate when double-rate audio mode is enabled.
00: Left-AGC decay time = 100 ms
01: Left-AGC decay time = 200 ms
10: Left-AGC decay time = 400 ms
11: Left-AGC decay time = 500 ms
(1) Time constants are valid when DRA is not enabled. The values would change if DRA is enabled.
Page 0/Register 27: Left-AGC Control Register B
BIT READ/ RESET DESCRIPTION
WRITE VALUE
D7 – D1 R/W 1111 111 Left-AGC Maximum Gain Allowed
0000 000: Maximum gain = 0 dB
0000 001: Maximum gain = 0.5 dB
0000 010: Maximum gain = 1 dB
…
1110 110: Maximum gain = 59 dB
1110 111 – 111 111: Maximum gain = 59.5 dB
D0 R/W 0 Reserved. Write only zero to this register bit.
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