Datasheet
Table Of Contents
- FEATURES
- APPLICATIONS
- DESCRIPTION
- DESCRIPTION (Continued)
- PIN ASSIGNMENTS
- ABSOLUTE MAXIMUM RATINGS
- PACKAGE THERMAL RATINGS
- SYSTEM THERMAL CHARACTERISTICS
- RECOMMENDED OPERATING CONDITIONS
- ELECTRICAL CHARACTERISTICS
- TYPICAL CHARACTERISTICS
- OVERVIEW
- HARDWARE RESET
- DIGITAL CONTROL SERIAL INTERFACE
- I2C CONTROL INTERFACE
- I2C BUS DEBUG IN A GLITCHED SYSTEM
- DIGITAL AUDIO DATA SERIAL INTERFACE
- RIGHT-JUSTIFIED MODE
- LEFT-JUSTIFIED MODE
- I2S MODE
- DSP MODE
- TDM DATA TRANSFER
- AUDIO DATA CONVERTERS
- AUDIO CLOCK GENERATION
- STEREO AUDIO ADC
- DIGITAL AUDIO PROCESSING FOR RECORD PATH
- AUTOMATIC GAIN CONTROL (AGC)
- STEREO AUDIO DAC
- DIGITAL AUDIO PROCESSING FOR PLAYBACK
- DIGITAL INTERPOLATION FILTER
- DELTA-SIGMA AUDIO DAC
- AUDIO DAC DIGITAL VOLUME CONTROL
- INCREASING DAC DYNAMIC RANGE
- ANALOG OUTPUT COMMON-MODE ADJUSTMENT
- AUDIO DAC POWER CONTROL
- AUDIO ANALOG INPUTS
- ANALOG INPUT BYPASS PATH FUNCTIONALITY
- ADC PGA SIGNAL BYPASS PATH FUNCTIONALITY
- INPUT IMPEDANCE AND VCM CONTROL
- MICBIAS GENERATION
- PASSIVE ANALOG BYPASS DURING POWER DOWN
- ANALOG FULLY DIFFERENTIAL LINE OUTPUT DRIVERS
- ANALOG HIGH-POWER OUTPUT DRIVERS
- SHORT-CIRCUIT OUTPUT PROTECTION
- JACK/HEADSET DETECTION
- CONTROL REGISTERS
- Output Stage Volume Controls
TLV320AIC3101
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........................................................................................................................................ SLAS520D – FEBRUARY 2007 – REVISED DECEMBER 2008
Page 0/Register 19: MIC1LP/LINE1LP to Left-ADC Control Register
BIT READ/ RESET DESCRIPTION
WRITE VALUE
D7 R/W 0 MIC1LP/LINE1LP Single-Ended vs Fully Differential Control. If MIC1LP/LINE1LP is selected to both left-
and right-ADC channels, both connections must use the same configuration (single-ended or fully
differential mode).
0: MIC1LP/LINE1LP is configured in single-ended mode.
1: MIC1LP/LINE1LP and MIC1LM/LINE1LM are configured in fully differential mode.
D6 – D3 R/W 1111 MIC1LP/LINE1LP Input Level Control for Left-ADC PGA Mix
Setting the input level control to one of the following gains automatically connects LINE1L to the left-ADC
PGA mix.
0000: Input level control gain = 0 dB
0001: Input level control gain = – 1.5 dB
0010: Input level control gain = – 3 dB
0011: Input level control gain = – 4.5 dB
0100: Input level control gain = – 6 dB
0101: Input level control gain = – 7.5 dB
0110: Input level control gain = – 9 dB
0111: Input level control gain = – 10.5 dB
1000: Input level control gain = – 12 dB
1001 – 1110: Reserved. Do not write these sequences.
1111: LINE1L is not connected to the left-ADC PGA.
D2 R/W 0 Left-ADC Channel Power Control
0: Left-ADC channel is powered down.
1: Left-ADC channel is powered up.
D1 – D0 R/W 00 Left-ADC PGA Soft-Stepping Control
00: Left-ADC PGA soft-stepping at once per f
S
01: Left-ADC PGA soft-stepping at once per two f
S
10 – 11: Left-ADC PGA soft-stepping is disabled.
Page 0/Register 20: Reserved Register
BIT READ/ RESET DESCRIPTION
WRITE VALUE
D7 – D0 R 0111 1000 Reserved. Do not write to this register.
Page 0/Register 21: MIC1RP/LINE1RP to Left-ADC Control Register
BIT READ/ RESET DESCRIPTION
WRITE VALUE
D7 R/W 0 MIC1RP/LINE1RP Single-Ended vs Fully Differential Control. If MIC1RP/LINE1RP is selected to both left-
and right-ADC channels, both connections must use the same configuration (single-ended or fully
differential mode).
0: MIC1RP/LINE1RP is configured in single-ended mode.
1: MIC1RP/LINE1RP and MIC1RM/LINE1RM are configured in fully differential mode.
D6 – D3 R/W 1111 MIC1RP/LINE1RP Input Level Control for Left-ADC PGA Mix
Setting the input level control to one of the following gains automatically connects LINE1R to the left-ADC
PGA mix.
0000: Input level control gain = 0 dB
0001: Input level control gain = – 1.5 dB
0010: Input level control gain = – 3 dB
0011: Input level control gain = – 4.5 dB
0100: Input level control gain = – 6 dB
0101: Input level control gain = – 7.5 dB
0110: Input level control gain = – 9 dB
0111: Input level control gain = – 10.5 dB
1000: Input level control gain = – 12 dB
1001 – 1110: Reserved. Do not write these sequences.
1111: LINE1R is not connected to the left-ADC PGA.
D2 – D0 R 000 Reserved. Write only zeros to these bits.
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