Datasheet
Table Of Contents
- FEATURES
- APPLICATIONS
- DESCRIPTION
- DESCRIPTION (Continued)
- PIN ASSIGNMENTS
- ABSOLUTE MAXIMUM RATINGS
- PACKAGE THERMAL RATINGS
- SYSTEM THERMAL CHARACTERISTICS
- RECOMMENDED OPERATING CONDITIONS
- ELECTRICAL CHARACTERISTICS
- TYPICAL CHARACTERISTICS
- OVERVIEW
- HARDWARE RESET
- DIGITAL CONTROL SERIAL INTERFACE
- I2C CONTROL INTERFACE
- I2C BUS DEBUG IN A GLITCHED SYSTEM
- DIGITAL AUDIO DATA SERIAL INTERFACE
- RIGHT-JUSTIFIED MODE
- LEFT-JUSTIFIED MODE
- I2S MODE
- DSP MODE
- TDM DATA TRANSFER
- AUDIO DATA CONVERTERS
- AUDIO CLOCK GENERATION
- STEREO AUDIO ADC
- DIGITAL AUDIO PROCESSING FOR RECORD PATH
- AUTOMATIC GAIN CONTROL (AGC)
- STEREO AUDIO DAC
- DIGITAL AUDIO PROCESSING FOR PLAYBACK
- DIGITAL INTERPOLATION FILTER
- DELTA-SIGMA AUDIO DAC
- AUDIO DAC DIGITAL VOLUME CONTROL
- INCREASING DAC DYNAMIC RANGE
- ANALOG OUTPUT COMMON-MODE ADJUSTMENT
- AUDIO DAC POWER CONTROL
- AUDIO ANALOG INPUTS
- ANALOG INPUT BYPASS PATH FUNCTIONALITY
- ADC PGA SIGNAL BYPASS PATH FUNCTIONALITY
- INPUT IMPEDANCE AND VCM CONTROL
- MICBIAS GENERATION
- PASSIVE ANALOG BYPASS DURING POWER DOWN
- ANALOG FULLY DIFFERENTIAL LINE OUTPUT DRIVERS
- ANALOG HIGH-POWER OUTPUT DRIVERS
- SHORT-CIRCUIT OUTPUT PROTECTION
- JACK/HEADSET DETECTION
- CONTROL REGISTERS
- Output Stage Volume Controls
TLV320AIC3101
SLAS520D – FEBRUARY 2007 – REVISED DECEMBER 2008 ........................................................................................................................................
www.ti.com
Page 0/Register 12: Audio Codec Digital Filter Control Register
BIT READ/ RESET DESCRIPTION
WRITE VALUE
D7 – D6 R/W 00 Left-ADC High-Pass Filter Control
00: Left-ADC high-pass filter disabled
01: Left-ADC high-pass filter – 3-dB frequency = 0.0045 × ADC f
S
10: Left-ADC high-pass filter – 3-dB frequency = 0.0125 × ADC f
S
11: Left-ADC high-pass filter – 3-dB frequency = 0.025 × ADC f
S
D5 – D4 R/W 00 Right-ADC High-Pass Filter Control
00: Right-ADC high-pass filter disabled
01: Right-ADC high-pass filter – 3-dB frequency = 0.0045 × ADC f
S
10: Right-ADC high-pass filter – 3-dB frequency = 0.0125 × ADC f
S
11: Right-ADC high-pass filter – 3-dB frequency = 0.025 × ADC f
S
D3 R/W 0 Left-DAC Digital Effects Filter Control
0: Left-DAC digital effects filter disabled (bypassed)
1: Left-DAC digital effects filter enabled
D2 R/W 0 Left-DAC De-Emphasis Filter Control
0: Left-DAC de-emphasis filter disabled (bypassed)
1: Left-DAC de-emphasis filter enabled
D1 R/W 0 Right-DAC Digital Effects Filter Control
0: Right-DAC digital effects filter disabled (bypassed)
1: Right-DAC digital effects filter enabled
D0 R/W 0 Right-DAC De-Emphasis Filter Control
0: Right-DAC de-emphasis filter disabled (bypassed)
1: Right-DAC de-emphasis filter enabled
Page 0/Register 13: Reserved
BIT READ/ RESET DESCRIPTION
WRITE VALUE
D7 – D0 R/W 0000 0000 Reserved. Write only 0000 0000 to this register.
52 Submit Documentation Feedback Copyright © 2007 – 2008, Texas Instruments Incorporated
Product Folder Link(s): TLV320AIC3101