Datasheet
Table Of Contents
- FEATURES
- APPLICATIONS
- DESCRIPTION
- DESCRIPTION (Continued)
- PIN ASSIGNMENTS
- ABSOLUTE MAXIMUM RATINGS
- PACKAGE THERMAL RATINGS
- SYSTEM THERMAL CHARACTERISTICS
- RECOMMENDED OPERATING CONDITIONS
- ELECTRICAL CHARACTERISTICS
- TYPICAL CHARACTERISTICS
- OVERVIEW
- HARDWARE RESET
- DIGITAL CONTROL SERIAL INTERFACE
- I2C CONTROL INTERFACE
- I2C BUS DEBUG IN A GLITCHED SYSTEM
- DIGITAL AUDIO DATA SERIAL INTERFACE
- RIGHT-JUSTIFIED MODE
- LEFT-JUSTIFIED MODE
- I2S MODE
- DSP MODE
- TDM DATA TRANSFER
- AUDIO DATA CONVERTERS
- AUDIO CLOCK GENERATION
- STEREO AUDIO ADC
- DIGITAL AUDIO PROCESSING FOR RECORD PATH
- AUTOMATIC GAIN CONTROL (AGC)
- STEREO AUDIO DAC
- DIGITAL AUDIO PROCESSING FOR PLAYBACK
- DIGITAL INTERPOLATION FILTER
- DELTA-SIGMA AUDIO DAC
- AUDIO DAC DIGITAL VOLUME CONTROL
- INCREASING DAC DYNAMIC RANGE
- ANALOG OUTPUT COMMON-MODE ADJUSTMENT
- AUDIO DAC POWER CONTROL
- AUDIO ANALOG INPUTS
- ANALOG INPUT BYPASS PATH FUNCTIONALITY
- ADC PGA SIGNAL BYPASS PATH FUNCTIONALITY
- INPUT IMPEDANCE AND VCM CONTROL
- MICBIAS GENERATION
- PASSIVE ANALOG BYPASS DURING POWER DOWN
- ANALOG FULLY DIFFERENTIAL LINE OUTPUT DRIVERS
- ANALOG HIGH-POWER OUTPUT DRIVERS
- SHORT-CIRCUIT OUTPUT PROTECTION
- JACK/HEADSET DETECTION
- CONTROL REGISTERS
- Output Stage Volume Controls
LEFT_LOP
RIGHT_LOP
LEFT_LOM
RIGHT_LOM
SW-L0
SW-R0
SW-L3
SW-R3
SW-L1
SW-R1
SW-L4
SW-R4
SW-L2
SW-R2
MIC1LP/LINE1LP
MIC1RP/LINE1RP
MIC1LM/LINE1LM
MIC1RM/LINE1RM
LINE1LP
LINE1RP
LINE1LM
LINE1RM
MIC2L/LINE2L/MICDET
MIC2R/LINE2R
LINE2L
LINE2R
B0174-01
TLV320AIC3101
www.ti.com
........................................................................................................................................ SLAS520D – FEBRUARY 2007 – REVISED DECEMBER 2008
Connecting the MIC1LP/LINE1LP input signal to the LEFT_LOP pin is done by closing SW-L1 and opening
SW-L0; this action is done by writing a 1 to page 0, register 108, bit D0. Connecting the MIC2LP/LINE2LP input
signal to the LEFT_LOP pin is done by closing SW-L2 and opening SW-L0; this action is done by writing a 1 to
page 0, register 108, bit D2. Connecting the MIC1LM/LINE1LM input signal to the LEFT_LOM pin is done by
closing SW-L4 and opening SW-L3; this action is done by writing a 1 to page 0, register 108, bit D1.
Connecting the MIC1RP/LINE1RP input signal to the RIGHT_LOP pin is done by closing SW-R1 and opening
SW-R0; this action is done by writing a 1 to page 0, register 108, bit D4. Connecting the MIC2RP/LINE2RP input
signal to the RIGHT_LOP pin is done by closing SW-R2 and opening SW-R0; this action is done by writing a 1 to
page 0, register 108, bit D6. Connecting MIC1RM/LINE1RM input signal to the RIGHT_LOM pin is done by
closing SW-R4 and opening SW-R3; this action is done by writing a 1 to page 0, register 108, bit D5. A diagram
of the passive analog bypass mode configuration is shown in Figure 30 .
In general, connecting two switches to the same output pin should be avoided, as this error shorts two input
signals together, and would likely cause distortion of the signal as the two signals are in contention. Poor
frequency response would also likely occur.
Figure 30. Passive Analog Bypass Mode Configuration
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