Datasheet

TLV320AIC3101
SLAS520D – FEBRUARY 2007 – REVISED DECEMBER 2008 ........................................................................................................................................ www.ti.com
A primary concern is proper operation of the codec at various sample rates with the limited MCLK frequencies
available in the system. This device includes a highly programmable PLL to accommodate such situations easily.
The integrated PLL can generate audio clocks from a wide variety of possible MCLK inputs, with particular focus
paid to the standard MCLK rates already widely used.
When the PLL is disabled,
f
S(ref)
= CLKDIV_IN/(128 × Q)
Where Q = 2, 3, … , 17
CLKDIV_IN can be MCLK or BCLK, selected by register 102, bits D7 – D6.
NOTE – when NCODEC = 1.5, 2.5, 3.5, 4.5, or 5.5, odd values of Q are not allowed. In this mode, MCLK can be
as high as 50 MHz, and f
S(ref)
should fall within 39 kHz to 53 kHz, inclusive.
When the PLL is enabled,
f
S(ref)
= (PLLCLK_IN × K × R)/(2048 × P), where
P = 1, 2, 3, … , 8
R = 1, 2, … , 16
K = J.D
J = 1, 2, 3, … , 63
D = 0000, 0001, 0002, 0003, … , 9998, 9999
PLLCLK_IN can be MCLK or BCLK, selected by Page 0, register 102, bits D5 – D4
P, R, J, and D are register programmable. J is the integer portion of K (the numbers to the left of the decimal
point), while D is the fractional portion of K (the numbers to the right of the decimal point, assuming four digits of
precision).
Examples:
If K = 8.5, then J = 8, D = 5000
If K = 7.12, then J = 7, D = 1200
If K = 14.03, then J = 14, D = 0300
If K = 6.0004, then J = 6, D = 0004
When the PLL is enabled and D = 0000, the following conditions must be satisfied to meet specified
performance:
2 MHz ≤ ( PLLCLK_IN/P ) ≤ 20 MHz
80 MHz ≤ (PLLCLK _IN × K × R/P ) ≤ 110 MHz
4 ≤ J ≤ 55
When the PLL is enabled and D ≠ 0000, the following conditions must be satisfied to meet specified performance:
10 MHz ≤ PLLCLK _IN/P ≤ 20 MHz
80 MHz ≤ PLLCLK _IN × K × R/P ≤ 110 MHz
4 ≤ J ≤ 11
R = 1
Example:
MCLK = 12 MHz and f
S(ref)
= 44.1 kHz
Select P = 1, R = 1, K = 7.5264, which results in J = 7, D = 5264
Example:
MCLK = 12 MHz and f
S(ref)
= 48 kHz
Select P = 1, R = 1, K = 8.192, which results in J = 8, D = 1920
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