Datasheet

A
udio Serial Bus Interface
I
2
C Serial
Co
ntrol Bus
Bias/
R
eference
MICBIAS
SCL
SDA
RESET
Volt
age Supplies
A
udio Clock
G
eneration
MCLK
LINE2L
P
GA
0/+
59.5dB
0.5
dB
S
teps
AD
C
+
+
+
+ + +
VCM
VCM
DAC
L
+
Volume
C
ontrol
E
ffects
DIN
DOUT
BCLK
WCLK
DINL
DINR
DOUTL
DOUTR
MIC2R/LINE2R
LINE2R
ADC
PGA
0/+59.5dB
0.5d
B
Steps
+
DAC
R
Volume
Co
ntrol
Effects
AGC
AGC
SW-D2
SW-D1
SW-D3
SW-D4
DVDD
DRVDD
DRVDD
DRVSS
DVSS
IOVDD
AVSS_ADC
AVDD_DAC
AVSS_DAC
HPROUT HPRCOM HPLCOM HPLOUT
LE
FT_LOP
LE
FT_LOM
LINE1LP LINE2LP
LINE1LM
L
INE1RM
S
W-L0
S
W-L1
SW-L2
SW-L4
SW
-L3
SW
-R4
S
W-R3
RIGHT_LOP
R
IGHT_LOM
LINE1RP LI
NE2RP
SW-R0
SW
-R1
SW-R2
B0151-01
MIC1RP/LINE1RP
MIC1RM/LINE1RM
L
INE1RP
LINE1RM
M
IC1LP/LINE1LP
MIC1LM/LINE1LM
LIN
E1LP
L
INE1LM
MIC2L/LINE2L/
MICDET
TLV320AIC3101
www.ti.com ........................................................................................................................................ SLAS520D – FEBRUARY 2007 – REVISED DECEMBER 2008
SIMPLIFIED BLOCK DIAGRAM
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