Datasheet

I
2
S MODE
BCLK
WCLK
1 1
0 0
T0151-01
1/fs
LSBMSB
LeftChannel
RightChannel
2 2
SDIN/SDOUT
n–1 n–1 n–1
1ClockBeforeMSB
n–2 n–2
n–3 n–3
DSP MODE
BCLK
WCLK
0 0
T0152-01
1/fs
LSB LSBLSB MSB MSB
LeftChannel
RightChannel
1 12 2
SDIN/SDOUT
n–1 n–1n–1n–2
n–3 n–3n–4
n–2
TDM DATA TRANSFER
TLV320AIC3101
www.ti.com ........................................................................................................................................ SLAS520D – FEBRUARY 2007 – REVISED DECEMBER 2008
In I
2
S mode, the MSB of the left channel is valid on the second rising edge of the bit clock after the falling edge
of the word clock. Similarly, the MSB of the right channel is valid on the second rising edge of the bit clock after
the rising edge of the word clock.
Figure 21. I
2
S Serial Data Bus Mode Operation
In DSP mode, the rising edge of the word clock starts the data transfer with the left-channel data first,
immediately followed by the right-channel data. Each data bit is valid on the falling edge of the bit clock.
Figure 22. DSP Serial Data Bus Mode Operation
Time-division multiplexed data transfer can be realized in any of the left- transfer modes if the 256-clock bit-clock
mode is selected, although it is recommended to be used in either left-justified mode or DSP mode. By changing
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