Datasheet

RIGHT-JUSTIFIED MODE
BCLK
WCLK
1
00
1
0
T0149-01
1/fs
LSBMSB
LeftChannel
RightChannel
2 2
SDIN/SDOUT
n–1 n–1n–2 n–2n–3
n–3
LEFT-JUSTIFIED MODE
BCLK
WCLK
1 1
0 00
T0150-01
1/fs
LSBMSB
LeftChannel
RightChannel
2 2
SDIN/SDOUT
n–1 n–1 n–1n–2 n–2 n–2n–3 n–3
TLV320AIC3101
SLAS520D – FEBRUARY 2007 – REVISED DECEMBER 2008 ........................................................................................................................................ www.ti.com
In right-justified mode, the LSB of the left channel is valid on the rising edge of the bit clock preceding the falling
edge of word clock. Similarly, the LSB of the right channel is valid on the rising edge of the bit clock preceding
the rising edge of the word clock.
Figure 19. Right-Justified Serial Data Bus Mode Operation
In left-justified mode, the MSB of the right channel is valid on the rising edge of the bit clock following the falling
edge of the word clock. Similarly, the MSB of the left channel is valid on the rising edge of the bit clock following
the rising edge of the word clock.
Figure 20. Left-Justified Serial Data Bus Mode Operation
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