Datasheet
Table Of Contents
- FEATURES
- APPLICATIONS
- DESCRIPTION
- DESCRIPTION (Continued)
- PIN ASSIGNMENTS
- ABSOLUTE MAXIMUM RATINGS
- PACKAGE THERMAL RATINGS
- SYSTEM THERMAL CHARACTERISTICS
- RECOMMENDED OPERATING CONDITIONS
- ELECTRICAL CHARACTERISTICS
- TYPICAL CHARACTERISTICS
- OVERVIEW
- HARDWARE RESET
- DIGITAL CONTROL SERIAL INTERFACE
- I2C CONTROL INTERFACE
- I2C BUS DEBUG IN A GLITCHED SYSTEM
- DIGITAL AUDIO DATA SERIAL INTERFACE
- RIGHT-JUSTIFIED MODE
- LEFT-JUSTIFIED MODE
- I2S MODE
- DSP MODE
- TDM DATA TRANSFER
- AUDIO DATA CONVERTERS
- AUDIO CLOCK GENERATION
- STEREO AUDIO ADC
- DIGITAL AUDIO PROCESSING FOR RECORD PATH
- AUTOMATIC GAIN CONTROL (AGC)
- STEREO AUDIO DAC
- DIGITAL AUDIO PROCESSING FOR PLAYBACK
- DIGITAL INTERPOLATION FILTER
- DELTA-SIGMA AUDIO DAC
- AUDIO DAC DIGITAL VOLUME CONTROL
- INCREASING DAC DYNAMIC RANGE
- ANALOG OUTPUT COMMON-MODE ADJUSTMENT
- AUDIO DAC POWER CONTROL
- AUDIO ANALOG INPUTS
- ANALOG INPUT BYPASS PATH FUNCTIONALITY
- ADC PGA SIGNAL BYPASS PATH FUNCTIONALITY
- INPUT IMPEDANCE AND VCM CONTROL
- MICBIAS GENERATION
- PASSIVE ANALOG BYPASS DURING POWER DOWN
- ANALOG FULLY DIFFERENTIAL LINE OUTPUT DRIVERS
- ANALOG HIGH-POWER OUTPUT DRIVERS
- SHORT-CIRCUIT OUTPUT PROTECTION
- JACK/HEADSET DETECTION
- CONTROL REGISTERS
- Output Stage Volume Controls
TLV320AIC3101
www.ti.com
........................................................................................................................................ SLAS520D – FEBRUARY 2007 – REVISED DECEMBER 2008
The bit clock (BCLK) is used to clock in and out the digital audio data across the serial bus. When in master
mode, this signal can be programmed in two further modes: continuous transfer mode, and 256-clock mode. In
continuous transfer mode, only the minimal number of bit clocks needed to transfer the audio data are generated,
so in general the number of bit clocks per frame is two times the data width. For example, if data width is chosen
as 16 bits, then 32 bit clocks are generated per frame. If the bit clock signal in master mode is to be used by a
PLL in another device, it is recommended that the 16-bit or 32-bit data-width selections be used. These cases
result in a low-jitter bit clock signal being generated, having frequencies of 32 f
S
or 64 f
S
. In the cases of 20-bit
and 24-bt data width in master mode, the bit clocks generated in each frame are not all of equal period, due to
the device not having a clean 40-f
S
or 48-f
S
clock signal readily available. The average frequency of the bit clock
signal is still accurate in these cases (being 40 f
S
or 48 f
S
), but the resulting clock signal has higher jitter than in
the 16-bit and 32-bit cases.
In 256-clock mode, a constant 256 bit clocks per frame are generated, independent of the data width chosen.
The TLV320AIC3101 further includes programmability to place the DOUT line in the high-impedance state during
all bit clocks when valid data is not being sent. By combining this capability with the ability to program at what bit
clock in a frame the audio data begins, time-division multiplexing (TDM) can be accomplished, resulting in
multiple codecs able to use a single audio serial data bus.
When the digital audio data serial interface is powered down while configured in master mode, the pins
associated with the interface are put into a high-impedance state.
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