Datasheet

T0146-01
WCLK
BCLK
SDOUT
SDIN
t (DO-BCLK)
d
t (WS)
d
t (WS)
d
t (DI)
S
t (DI)
h
TLV320AIC3101
SLAS520D – FEBRUARY 2007 – REVISED DECEMBER 2008 ........................................................................................................................................ www.ti.com
All specifications at 25 ° C, DVDD = 1.8 V.
IOVDD = 1.1 V IOVDD = 3.3 V
PARAMETER UNIT
MIN MAX MIN MAX
t
d
(WS) ADWS/WCLK delay time 50 15 ns
t
d
(DO-BCLK) BCLK to DOUT delay time 50 15 ns
t
s
(DI) DIN setup time 10 6 ns
t
h
(DI) DIN hold time 10 6 ns
t
r
Rise time 30 10 ns
t
f
Fall time 30 10 ns
NOTE: All timing specifications are measured at characterization but not tested at final test.
Figure 2. DSP Timing in Master Mode
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