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Table Of Contents

FEATURES

APPLICATIONS

DESCRIPTION

TLV320AIC3101

www.ti.com

........................................................................................................................................ SLAS520D – FEBRUARY 2007 – REVISED DECEMBER 2008

LOW-POWER STEREO AUDIO CODEC FOR PORTABLE AUDIO/TELEPHONY

• Low Power: 14-mW Stereo 48-kHz Playback

With 3.3-V Analog Supply

• Stereo Audio DAC

• Ultralow-Power Mode With Passive Analog

– 102-dBA Signal-to-Noise Ratio

Bypass

– 16/20/24/32-Bit Data

• Programmable Input/Output Analog Gains

– Supports SampleRates From 8 kHz to 96

• Automatic Gain Control (AGC) for Record

kHz

• Programmable Microphone Bias Level

– 3D/Bass/Treble/EQ/De-Emphasis Effects

• Programmable PLL for Flexible Clock

– Flexible Power Saving Modes and

Generation

Performance are Available

• I

C Control Bus

• Stereo Audio ADC

• Audio Serial Data Bus Supports I

– 92-dBA Signal-to-Noise Ratio

Left/Right-Justified, DSP, and TDM Modes

– Supports Sample Rates From 8 kHz to 96

• Extensive Modular Power Control

kHz

• Power Supplies:

– Digital Signal Processing and Noise

Filtering Available During Record – Analog: 2.7 V – 3.6 V.

• Six Audio Input Pins – Digital Core: 1.525 V – 1.95 V

– One Stereo Pair of Single-Ended Inputs – Digital I/O: 1.1 V – 3.6 V

– One Stereo Pair of Fully Differential Inputs • Package: 5-mm × 5-mm 32-Pin QFN

• Six Audio Output Drivers

– Stereo Fully Differential or Single-Ended

• Digital Cameras

Headphone Drivers

• Smart Cellular Phones

– Fully Differential Stereo Line Outputs

– Stereo 8- Ω , 500-mW/Channel Speaker Drive

Capability

The TLV320AIC3101 is a low-power stereo audio codec with stereo headphone amplifier, as well as multiple

inputs and outputs that are programmable in single-ended or fully differential configurations. Extensive

analog supply, making it ideal for portable battery-powered audio and telephony applications.

The record path of the TLV320AIC3101 contains integrated microphone bias, digitally controlled stereo

microphone preamplifier, and automatic gain control (AGC), with mix/mux capability among the multiple analog

inputs. Programmable filters are available during record which can remove audible noise that can occur during

optical zooming in digital cameras. The playback path includes mix/mux capability from the stereo DAC and

selected inputs, through programmable volume controls, to the various outputs.

The TLV320AIC3101 contains four high-power output drivers as well as two fully differential output drivers. The

high-power output drivers are capable of driving a variety of load configurations, including up to four channels of

single-ended 16- Ω headphones using ac-coupling capacitors, or stereo 16- Ω headphones in a capless output

configuration. In addition, pairs of drivers can be used to drive 8- Ω speakers in a BTL configuration at 500 mW

per channel.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (95 pages)

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TLV320AIC3101 www.ti.com ........................................................................................................................................
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TLV320AIC3101 SLAS520D – FEBRUARY 2007 – REVISED DECEMBER 2008 ........................................................................................................................................ www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
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TLV320AIC3101 SLAS520D – FEBRUARY 2007 – REVISED DECEMBER 2008 ........................................................................................................................................ www.ti.
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TLV320AIC3101 www.ti.com ........................................................................................................................................ SLAS520D – FEBRUARY 2007 – REVISED DECEMBER 2008 Table 1. TERMINAL FUNCTIONS TERMINAL DESCRIPTION NAME QFN NO. I/O AVDD 25 — Analog DAC voltage supply, 2.7 V–3.
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TLV320AIC3101 SLAS520D – FEBRUARY 2007 – REVISED DECEMBER 2008 ........................................................................................................................................ www.ti.com ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) TJ Max RθJA (1) (2) (2) VALUE UNIT AVDD to AVSS, DRVDD to DRVSS –0.3 to 3.9 V AVDD to DRVSS –0.3 to 3.9 V IOVDD to DVSS –0.3 to 3.9 V DVDD to DVSS –0.3 to 2.5 V AVDD to DRVDD –0.1 to 0.
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TLV320AIC3101 www.ti.com ........................................................................................................................................ SLAS520D – FEBRUARY 2007 – REVISED DECEMBER 2008 ELECTRICAL CHARACTERISTICS At 25°C, AVDD_DAC = DRVDD = IOVDD = 3.3 V, DVDD = 1.
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TLV320AIC3101 SLAS520D – FEBRUARY 2007 – REVISED DECEMBER 2008 ........................................................................................................................................ www.ti.com ELECTRICAL CHARACTERISTICS (continued) At 25°C, AVDD_DAC = DRVDD = IOVDD = 3.3 V, DVDD = 1.8 V, fS = 48 kHz, 16-bit audio data (unless otherwise noted) PARAMETER TEST CONDITIONS MIN Programmable setting = 2 V 2.3 UNIT 2.455 2.7 V DRVDD – 0.
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TLV320AIC3101 www.ti.com ........................................................................................................................................ SLAS520D – FEBRUARY 2007 – REVISED DECEMBER 2008 ELECTRICAL CHARACTERISTICS (continued) At 25°C, AVDD_DAC = DRVDD = IOVDD = 3.3 V, DVDD = 1.
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TLV320AIC3101 SLAS520D – FEBRUARY 2007 – REVISED DECEMBER 2008 ........................................................................................................................................ www.ti.com ELECTRICAL CHARACTERISTICS (continued) At 25°C, AVDD_DAC = DRVDD = IOVDD = 3.3 V, DVDD = 1.8 V, fS = 48 kHz, 16-bit audio data (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT CURRENT CONSUMPTION – DRVDD = AVDD_DAC = IOVDD = 3.3 V, DVDD = 1.
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TLV320AIC3101 www.ti.com ........................................................................................................................................ SLAS520D – FEBRUARY 2007 – REVISED DECEMBER 2008 AUDIO DATA SERIAL INTERFACE TIMING DIAGRAMS All specifications at 25°C, DVDD = 1.8 V. WCLK td(WS) BCLK td(DO-WS) td(DO-BCLK) SDOUT tS(DI) th(DI) SDIN T0145-01 PARAMETER IOVDD = 1.1 V MIN MAX IOVDD = 3.
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TLV320AIC3101 SLAS520D – FEBRUARY 2007 – REVISED DECEMBER 2008 ........................................................................................................................................ www.ti.com All specifications at 25°C, DVDD = 1.8 V. WCLK td(WS) td(WS) BCLK td(DO-BCLK) SDOUT tS(DI) th(DI) SDIN T0146-01 PARAMETER IOVDD = 1.1 V MIN MAX IOVDD = 3.
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TLV320AIC3101 www.ti.com ........................................................................................................................................ SLAS520D – FEBRUARY 2007 – REVISED DECEMBER 2008 All specifications at 25°C, DVDD = 1.8 V. WCLK tS(WS) th(WS) tH(BCLK) BCLK td(DO-WS) tL(BCLK) td(DO-BCLK) SDOUT tS(DI) th(DI) SDIN T0145-02 PARAMETER IOVDD = 1.1 V MIN IOVDD = 3.
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TLV320AIC3101 SLAS520D – FEBRUARY 2007 – REVISED DECEMBER 2008 ........................................................................................................................................ www.ti.com All specifications at 25°C, DVDD = 1.8 V. WCLK tS(WS) tS(WS) th(WS) th(WS) tL(BCLK) BCLK td(DO-BCLK) tH(BCLK) SDOUT tS(DI) th(DI) SDIN T0146-02 PARAMETER IOVDD = 1.1 V MIN IOVDD = 3.
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TLV320AIC3101 www.ti.com ........................................................................................................................................ SLAS520D – FEBRUARY 2007 – REVISED DECEMBER 2008 TYPICAL CHARACTERISTICS THD − Total Harmonic Distortion − dB 0 Load = 16 Ω AC-Coupled −10 HPL DRVDD = 2.7 V −20 −30 HPL DRVDD = 3.3 V HPR DRVDD = 2.7 V HPR DRVDD = 3.3 V −40 −50 HPR DRVDD = 3.6 V −60 HPL DRVDD = 3.
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TLV320AIC3101 SLAS520D – FEBRUARY 2007 – REVISED DECEMBER 2008 ........................................................................................................................................ www.ti.com TYPICAL CHARACTERISTICS (continued) 0 −20 Amplitude − dB −40 −60 −80 −100 −120 −140 −160 0 2 4 6 8 10 12 14 16 18 20 f − Frequency − kHz G003 Figure 7.
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TLV320AIC3101 www.ti.com ........................................................................................................................................ SLAS520D – FEBRUARY 2007 – REVISED DECEMBER 2008 TYPICAL CHARACTERISTICS (continued) THD − Total Harmonic Distortion − dB 0 Load = 8 Ω −10 −20 DRVDD = 2.7 V −30 DRVDD = 3.3 V DRVDD = 3.6 V −40 −50 −60 −70 −80 −90 0 100 200 300 400 500 600 P − Speaker Power − W G005 Figure 9.
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TLV320AIC3101 SLAS520D – FEBRUARY 2007 – REVISED DECEMBER 2008 ........................................................................................................................................ www.ti.com TYPICAL CHARACTERISTICS (continued) 0.85 Left ADC 0.8 0.75 Right ADC Gain Error (dB) 0.7 0.65 0.6 0.55 0.5 0.45 0.4 0 10 20 30 40 PGA Setting (dB) 50 60 70 G009 Figure 11. ADC Gain Error vs PGA Gain Setting 3.6 MICBIAS Output Voltage − V 3.4 3.2 MICBIAS = AVDD 3.0 2.8 2.6 MICBIAS = 2.
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TLV320AIC3101 www.ti.com ........................................................................................................................................ SLAS520D – FEBRUARY 2007 – REVISED DECEMBER 2008 TYPICAL CHARACTERISTICS (continued) 3.2 MICBIAS Output Voltage − V 3.0 MICBIAS = AVDD 2.8 2.6 MICBIAS = 2.5 V 2.4 2.2 MICBIAS = 2 V 2.0 1.8 −45 −35 −25 −15 −5 5 15 25 35 45 55 65 TA − Ambient Temperature − °C 75 85 G008 Figure 13.
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TLV320AIC3101 SLAS520D – FEBRUARY 2007 – REVISED DECEMBER 2008 ........................................................................................................................................ www.ti.com TYPICAL CHARACTERISTICS (continued) TYPICAL CIRCUIT CONFIGURATION IOVDD DSP or Apps Processor 0.1 mF AVDD_DAC DRVDD DRVDD MIC1LP/LINE1LP MIC1LM/LINE1LM 1 kW A AVDD (2.7 V–3.6 V) 0.1 mF 0.1 mF 0.1 mF 1 mF 0.1 mF 0.47 mF FM Tuner MIC2L/LINE2L/MICDET MIC2R/LINE2R TLV320AIC3101 0.
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TLV320AIC3101 www.ti.com ........................................................................................................................................ SLAS520D – FEBRUARY 2007 – REVISED DECEMBER 2008 TYPICAL CHARACTERISTICS (continued) IOVDD DSP or Apps Processor AVDD_DAC DRVDD DRVDD MIC1LP/LINE1LP MIC1LM/LINE1LM 1 kW A AVDD (2.7 V–3.6 V) 0.1 mF 1 mF 1 mF 0.1 mF 0.47 mF FM Tuner MIC2L/LINE2L/MICDET MIC2R/LINE2R TLV320AIC3101 0.47 mF IOVDD MIC1RP/LINE1RP 1.525 V–1.95 V 0.
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TLV320AIC3101 SLAS520D – FEBRUARY 2007 – REVISED DECEMBER 2008 ........................................................................................................................................ www.ti.com OVERVIEW The TLV320AIC3101 is a highly flexible, low-power, stereo audio codec with extensive feature integration, intended for applications in smartphones, PDAs, and portable computing, communication, and entertainment applications.
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TLV320AIC3101 www.ti.com ........................................................................................................................................ SLAS520D – FEBRUARY 2007 – REVISED DECEMBER 2008 SDA tHD-STA ³ 0.9 ms SCL tSU-STA ³ 0.9 ms tSU-STO ³ 0.9 ms tHD-STA ³ 0.9 ms S Sr P S T0114-02 2 Figure 16. I C Interface Timing Communication on the I2C bus always takes place between two devices, one acting as the master and the other acting as the slave.
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TLV320AIC3101 SLAS520D – FEBRUARY 2007 – REVISED DECEMBER 2008 ........................................................................................................................................ www.ti.com The TLV320AIC3101 also responds to and acknowledges a general call, which consists of the master issuing a command with a slave-address byte of 00h.
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TLV320AIC3101 www.ti.com ........................................................................................................................................ SLAS520D – FEBRUARY 2007 – REVISED DECEMBER 2008 The bit clock (BCLK) is used to clock in and out the digital audio data across the serial bus. When in master mode, this signal can be programmed in two further modes: continuous transfer mode, and 256-clock mode.
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TLV320AIC3101 SLAS520D – FEBRUARY 2007 – REVISED DECEMBER 2008 ........................................................................................................................................ www.ti.com RIGHT-JUSTIFIED MODE In right-justified mode, the LSB of the left channel is valid on the rising edge of the bit clock preceding the falling edge of word clock. Similarly, the LSB of the right channel is valid on the rising edge of the bit clock preceding the rising edge of the word clock.
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TLV320AIC3101 www.ti.com ........................................................................................................................................ SLAS520D – FEBRUARY 2007 – REVISED DECEMBER 2008 I2S MODE In I2S mode, the MSB of the left channel is valid on the second rising edge of the bit clock after the falling edge of the word clock. Similarly, the MSB of the right channel is valid on the second rising edge of the bit clock after the rising edge of the word clock.
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TLV320AIC3101 SLAS520D – FEBRUARY 2007 – REVISED DECEMBER 2008 ........................................................................................................................................ www.ti.com the programmable offset, the bit clock in each frame where the data begins can be changed, and the serial data output driver (DOUT) can also be programmed to the high-impedance state during all bit clocks except when valid data is being put onto the bus.
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TLV320AIC3101 www.ti.com ........................................................................................................................................ SLAS520D – FEBRUARY 2007 – REVISED DECEMBER 2008 The sampling rate of the ADC and DAC can be set to fS(ref)/NCODEC or 2 × fS(ref)/NCODEC, with NCODEC being 1, 1.5, 2, 2.5, 3, 3.5, 4, 4.5, 5, 5.5, or 6 for both the NDAC and NADC settings.
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TLV320AIC3101 SLAS520D – FEBRUARY 2007 – REVISED DECEMBER 2008 ........................................................................................................................................ www.ti.com A primary concern is proper operation of the codec at various sample rates with the limited MCLK frequencies available in the system. This device includes a highly programmable PLL to accommodate such situations easily.
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TLV320AIC3101 www.ti.com ........................................................................................................................................ SLAS520D – FEBRUARY 2007 – REVISED DECEMBER 2008 The following table lists several example cases of typical MCLK rates and how to program the PLL to achieve fS(ref) = 44.1 kHz or 48 kHz. fS(ref) = 44.1 kHz MCLK (MHz) P R J 2.8224 1 1 32 D 0 ACHIEVED fS(ref) 44,100 % ERROR 0 5.
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TLV320AIC3101 SLAS520D – FEBRUARY 2007 – REVISED DECEMBER 2008 ........................................................................................................................................ www.ti.com power down, the PGA soft-steps the volume to mute before shutting down. A read-only flag is set whenever the gain applied by PGA equals the desired value set by the register. The soft-stepping control can also be disabled by programming a register bit.
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TLV320AIC3101 BCLK WCLK DIN DOUT www.ti.com ........................................................................................................................................ SLAS520D – FEBRUARY 2007 – REVISED DECEMBER 2008 AGC DINR DINL DOUTL DOUTR Digital Audio Data Serial Interface DAC Powered Down Record Path SW-D2 Left-Channel Analog Inputs + PGA 0 dB–59.5 dB, 0.
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TLV320AIC3101 SLAS520D – FEBRUARY 2007 – REVISED DECEMBER 2008 ........................................................................................................................................ www.ti.com Decay time determines how quickly the PGA gain is increased when the input signal is too low. It can be varied in the range from 0.05 s to 22.4 s.
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TLV320AIC3101 www.ti.com ........................................................................................................................................ SLAS520D – FEBRUARY 2007 – REVISED DECEMBER 2008 Input Signal Output Signal Target Level AGC Gain Decay Time Attack Time W0002-01 Figure 26. Typical Operation of the AGC Algorithm During Speech Recording Note that the time constants here are correct when the ADC is not in double-rate audio mode.
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TLV320AIC3101 SLAS520D – FEBRUARY 2007 – REVISED DECEMBER 2008 ........................................................................................................................................ www.ti.com DIGITAL AUDIO PROCESSING FOR PLAYBACK The DAC channel consists of optional filters for de-emphasis and bass, treble, midrange level adjustment, speaker equalization, and 3-D effects processing.
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TLV320AIC3101 www.ti.com ........................................................................................................................................ SLAS520D – FEBRUARY 2007 – REVISED DECEMBER 2008 Table 4.
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TLV320AIC3101 SLAS520D – FEBRUARY 2007 – REVISED DECEMBER 2008 ........................................................................................................................................ www.ti.com DELTA-SIGMA AUDIO DAC The stereo audio DAC incorporates a third-order multibit delta-sigma modulator followed by an analog reconstruction filter. The DAC provides high-resolution, low-noise performance, using oversampling and noise shaping techniques.
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TLV320AIC3101 www.ti.com ........................................................................................................................................ SLAS520D – FEBRUARY 2007 – REVISED DECEMBER 2008 Table 5. Appropriate Settings CM SETTING RECOMMENDED AVDD, DRVDD RECOMMENDED DVDD 1.35 2.7 V–3.6 V 1.525 V–1.95 V 1.5 3 V–3.6 V 1.65 V–1.95 V 1.65 V 3.3 V–3.6 V 1.8 V–1.95 V 1.8 V 3.6 V 1.
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TLV320AIC3101 SLAS520D – FEBRUARY 2007 – REVISED DECEMBER 2008 ........................................................................................................................................ www.ti.com ANALOG INPUT BYPASS PATH FUNCTIONALITY The TLV320AIC3101 includes the additional ability to route some analog input signals past the integrated data converters, for mixing with other analog signals and then direct connection to the output drivers.
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TLV320AIC3101 www.ti.com ........................................................................................................................................ SLAS520D – FEBRUARY 2007 – REVISED DECEMBER 2008 Connecting the MIC1LP/LINE1LP input signal to the LEFT_LOP pin is done by closing SW-L1 and opening SW-L0; this action is done by writing a 1 to page 0, register 108, bit D0.
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TLV320AIC3101 SLAS520D – FEBRUARY 2007 – REVISED DECEMBER 2008 ........................................................................................................................................ www.ti.com ANALOG FULLY DIFFERENTIAL LINE OUTPUT DRIVERS The TLV320AIC3101 has two fully differential line output drivers, each capable of driving a 10-kΩ differential load. The output stage design leading to the fully differential line output drivers is shown in Figure 31 and Figure 32.
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TLV320AIC3101 www.ti.com ........................................................................................................................................ SLAS520D – FEBRUARY 2007 – REVISED DECEMBER 2008 PGA_L 0 dB to –78 dB PGA_R 0 dB to –78 dB + DAC_L1 0 dB to –78 dB DAC_R1 0 dB to –78 dB B0158-01 Figure 32.
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TLV320AIC3101 SLAS520D – FEBRUARY 2007 – REVISED DECEMBER 2008 ........................................................................................................................................ www.ti.com 5.
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TLV320AIC3101 www.ti.com ........................................................................................................................................ SLAS520D – FEBRUARY 2007 – REVISED DECEMBER 2008 The high-power output drivers include additional circuitry to avoid artifacts on the audio output during power-on and power-off transient conditions.
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TLV320AIC3101 SLAS520D – FEBRUARY 2007 – REVISED DECEMBER 2008 ........................................................................................................................................ www.ti.com MICBIAS g Stereo s AVDD s MIC2L/LINE2L/MICDET To Detection Block MIC2R g Cellular MIC PreAmp s m HPLOUT Stereo + Cellular g m s Pwr Amp s HPROUT m = mic s = ear speaker g = ground/vcm Pwr Amp HPRCOM HPLCOM Pwr Amp To Detection Block 1.35 V B0243-02 Figure 34.
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TLV320AIC3101 www.ti.com ........................................................................................................................................ SLAS520D – FEBRUARY 2007 – REVISED DECEMBER 2008 An output configuration for the case of the outputs driving fully differential stereo headphones is shown in Figure 36.
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TLV320AIC3101 SLAS520D – FEBRUARY 2007 – REVISED DECEMBER 2008 ........................................................................................................................................ www.ti.com Page 0/Register 2: Codec Sample Rate Select Register BIT D7–D4 READ/ WRITE R/W RESET VALUE 0000 D3–D0 R/W 0000 (1) DESCRIPTION ADC Sample Rate Select (1) 0000: ADC fS = fS(ref)/1 0001: ADC fS = fS(ref)/1.5 0010: ADC fS = fS(ref)/2 0011: ADC fS = fS(ref)/2.
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TLV320AIC3101 www.ti.com ........................................................................................................................................ SLAS520D – FEBRUARY 2007 – REVISED DECEMBER 2008 Page 0/Register 4: PLL Programming Register B BIT D7–D2 READ/ WRITE R/W RESET VALUE 0000 01 D1–D0 R/W 00 DESCRIPTION PLL J Value 0000 00: Reserved. Do not write this sequence.
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TLV320AIC3101 SLAS520D – FEBRUARY 2007 – REVISED DECEMBER 2008 ........................................................................................................................................ www.ti.com Page 0/Register 8: Audio Serial Data Interface Control Register A BIT D7 READ/ WRITE R/W RESET VALUE 0 D6 R/W 0 D5 R/W 0 D4 R/W 0 D3 D2 R/W R/W 0 0 D1–D0 R/W 00 DESCRIPTION Bit Clock Directional Control 0: BCLK is an input (slave mode). 1: BCLK is an output (master mode).
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TLV320AIC3101 www.ti.com ........................................................................................................................................ SLAS520D – FEBRUARY 2007 – REVISED DECEMBER 2008 Page 0/Register 19: MIC1LP/LINE1LP to Left-ADC Control Register BIT D7 READ/ WRITE R/W RESET VALUE 0 D6–D3 R/W 1111 D2 R/W 0 D1–D0 R/W 00 DESCRIPTION MIC1LP/LINE1LP Single-Ended vs Fully Differential Control.
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TLV320AIC3101 SLAS520D – FEBRUARY 2007 – REVISED DECEMBER 2008 ........................................................................................................................................ www.ti.com Page 0/Register 22: MIC1RP/LINE1RP to Right-ADC Control Register BIT D7 READ/ WRITE R/W RESET VALUE 0 D6–D3 R/W 1111 D2 R/W 0 D1–D0 R/W 00 BIT READ/ WRITE R/W RESET VALUE 0111 1000 DESCRIPTION MIC1RP/LINE1RP Single-Ended vs Fully Differential Control.
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TLV320AIC3101 www.ti.com ........................................................................................................................................ SLAS520D – FEBRUARY 2007 – REVISED DECEMBER 2008 Page 0/Register 25: MICBIAS Control Register BIT D7–D6 READ/ WRITE R/W RESET VALUE 00 D5–D3 D2–D0 R R 000 XXX BIT D7 READ/ WRITE R/W RESET VALUE 0 D6–D4 R/W 000 D3–D2 R/W 00 D1–D0 R/W 00 DESCRIPTION MICBIAS Level Control 00: MICBIAS output is powered down.
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TLV320AIC3101 SLAS520D – FEBRUARY 2007 – REVISED DECEMBER 2008 ........................................................................................................................................ www.ti.com Page 0/Register 34: Left-AGC Noise Gate Debounce Register BIT D7–D3 READ/ WRITE R/W RESET VALUE 0000 0 D2–D0 R/W 000 (1) DESCRIPTION Left-AGC Noise Detection Debounce Control These times (1) are not accurate when double-rate audio mode is enabled. 0000 0: Debounce = 0 ms 0000 1: Debounce = 0.
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TLV320AIC3101 SLAS520D – FEBRUARY 2007 – REVISED DECEMBER 2008 ........................................................................................................................................ www.ti.com Page 0/Register 38: High-Power Output Driver Control Register BIT D7–D6 D5–D3 READ/ WRITE R R/W RESET VALUE 00 000 D2 R/W 0 D1 R/W 0 D0 R 0 DESCRIPTION Reserved. Write only zeros to these bits.
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TLV320AIC3101 SLAS520D – FEBRUARY 2007 – REVISED DECEMBER 2008 ........................................................................................................................................ www.ti.com Output Stage Volume Controls A basic analog volume control with range from 0 dB to –78 dB and mute is replicated multiple times in the output stage network, connected to each of the analog signals that route to the output stage.
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TLV320AIC3101 www.ti.com ........................................................................................................................................ SLAS520D – FEBRUARY 2007 – REVISED DECEMBER 2008 Page 0/Register 46: PGA_L to HPLOUT Volume Control Register BIT D7 READ/ WRITE R/W RESET VALUE 0 D6–D0 R/W 000 0000 BIT D7 READ/ WRITE R/W RESET VALUE 0 D6–D0 R/W 000 0000 DESCRIPTION PGA_L Output Routing Control 0: PGA_L is not routed to HPLOUT. 1: PGA_L is routed to HPLOUT.
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TLV320AIC3101 www.ti.com ........................................................................................................................................ SLAS520D – FEBRUARY 2007 – REVISED DECEMBER 2008 Page 0/Register 57: DAC_R1 to HPLCOM Volume Control Register BIT D7 READ/ WRITE R/W RESET VALUE 0 DESCRIPTION D6–D0 R/W 000 0000 BIT D7–D4 READ/ WRITE R/W RESET VALUE 0000 D3 R/W 0 D2 R/W 1 D1 R 1 D0 R/W 0 DAC_R1 Output Routing Control 0: DAC_R1 is not routed to HPLCOM.
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TLV320AIC3101 SLAS520D – FEBRUARY 2007 – REVISED DECEMBER 2008 ........................................................................................................................................ www.ti.com Page 0/Register 63: PGA_R to HPROUT Volume Control Register BIT D7 READ/ WRITE R/W RESET VALUE 0 DESCRIPTION D6–D0 R/W 000 0000 BIT D7 READ/ WRITE R/W RESET VALUE 0 D6–D0 R/W 000 0000 PGA_R Output Routing Control 0: PGA_R is not routed to HPROUT. 1: PGA_R is routed to HPROUT.
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TLV320AIC3101 www.ti.com ........................................................................................................................................ SLAS520D – FEBRUARY 2007 – REVISED DECEMBER 2008 Page 0/Register 86: LEFT_LOP/M Output Level Control Register BIT D7–D4 READ/ WRITE R/W RESET VALUE 0000 D3 R/W 0 D2 D1 R R 0 1 D0 R 0 DESCRIPTION LEFT_LOP/M Output Level Control 0000: Output level control = 0 dB 0001: Output level control = 1 dB 0010: Output level control = 2 dB ...
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TLV320AIC3101 www.ti.com ........................................................................................................................................ SLAS520D – FEBRUARY 2007 – REVISED DECEMBER 2008 Page 0/Register 101: Clock Register BIT D7–D1 D0 READ/ WRITE R R/W RESET VALUE 0000 000 0 DESCRIPTION Reserved. Write only zeros to these bits.
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TLV320AIC3101 SLAS520D – FEBRUARY 2007 – REVISED DECEMBER 2008 ........................................................................................................................................ www.ti.com Page 0/Register 104: Left-AGC New Programmable Decay Time Register (1) BIT D7 READ/ WRITE R/W RESET VALUE 0 D6–D5 R/W 00 D4–D2 R/W 000 D1–D0 R/W 00 (1) DESCRIPTION Decay Time Register Selection 0: Decay time for the left AGC is generated from page 0, register 26.
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TLV320AIC3101 www.ti.com ........................................................................................................................................ SLAS520D – FEBRUARY 2007 – REVISED DECEMBER 2008 Page 0/Register 106: Right-AGC New Programmable Decay Time Register (1) BIT D7 READ/ WRITE R/W RESET VALUE 0 D6–D5 R/W 00 D4–D2 R/W 000 D1–D0 R/W 00 (1) DESCRIPTION Decay Time Register Selection 0: Decay time for the right AGC is generated from page 0, register 29.
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TLV320AIC3101 SLAS520D – FEBRUARY 2007 – REVISED DECEMBER 2008 ........................................................................................................................................ www.ti.com Page 0/Register 108: Passive Analog Signal Bypass Selection During Power Down Register (1) BIT (1) D7 D6 READ/ WRITE R/W R/W RESET VALUE 0 0 D5 R/W 0 D4 R/W 0 D3 D2 R/W R/W 0 0 D1 R/W 0 D0 R/W 0 DESCRIPTION Reserved. Write only zero to this bit.
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TLV320AIC3101 www.ti.com ........................................................................................................................................ SLAS520D – FEBRUARY 2007 – REVISED DECEMBER 2008 Table 9.35.
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TLV320AIC3101 SLAS520D – FEBRUARY 2007 – REVISED DECEMBER 2008 ........................................................................................................................................ www.ti.
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TLV320AIC3101 SLAS520D – FEBRUARY 2007 – REVISED DECEMBER 2008 ........................................................................................................................................ www.ti.
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TLV320AIC3101 www.ti.com ........................................................................................................................................
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TLV320AIC3101 SLAS520D – FEBRUARY 2007 – REVISED DECEMBER 2008 ........................................................................................................................................ www.ti.
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TLV320AIC3101 www.ti.com ........................................................................................................................................
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TLV320AIC3101 SLAS520D – FEBRUARY 2007 – REVISED DECEMBER 2008 ........................................................................................................................................ www.ti.
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TLV320AIC3101 www.ti.com ........................................................................................................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 27-Jul-2013 continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
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PACKAGE MATERIALS INFORMATION www.ti.com 27-Jul-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TLV320AIC3101IRHBR VQFN RHB 32 2500 330.0 12.4 5.3 5.3 1.5 8.0 12.0 Q2 TLV320AIC3101IRHBR VQFN RHB 32 2500 330.0 12.4 5.3 5.3 1.5 8.0 12.0 Q2 TLV320AIC3101IRHBT VQFN RHB 32 250 180.0 12.4 5.3 5.3 1.5 8.0 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 27-Jul-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TLV320AIC3101IRHBR VQFN RHB 32 2500 367.0 367.0 35.0 TLV320AIC3101IRHBR VQFN RHB 32 2500 338.1 338.1 20.6 TLV320AIC3101IRHBT VQFN RHB 32 250 210.0 185.0 35.0 TLV320AIC3101IRHBT VQFN RHB 32 250 210.0 185.0 35.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.