Datasheet

TLV320AIC3100
SLAS667A –NOVEMBER 2009–REVISED MAY 2012 www.ti.com
Page 0 / Register 65: DAC Left Volume Control
READ/ RESET
BIT DESCRIPTION
WRITE VALUE
D7–D0 R/W 0000 0000 0111 1111–0111 0001: Reserved. Do not write these sequences to these bits.
0011 0000 : Left-channel DAC digital gain = 24 dB
0010 1111: Left-channel DAC digital gain = 23.5 dB
0010 1110: Left-channel DAC digital gain = 23 dB
...
0000 0001: Left-channel DAC digital gain = 0.5 dB
0000 0000: Left-channel DAC digital gain = 0 dB
1111 1111: Left-channel DAC digital gain = –0.5 dB
...
1000 0010: Left-channel DAC digital gain = –63 dB
1000 0001: Left-channel DAC digital gain = –63.5 dB
1000 0000: Reserved. Do not use.
Page 0 / Register 66: DAC Right Volume Control
READ/ RESET
BIT DESCRIPTION
WRITE VALUE
D7–D0 R/W 0000 0000 0111 1111–0111 0001: Reserved. Do not write these sequences to these bits.
0011 0000 : Left-channel DAC digital gain = 24 dB
0010 1111: Left-channel DAC digital gain = 23.5 dB
0010 1110: Left-channel DAC digital gain = 23 dB
...
0000 0001: Left-channel DAC digital gain = 0.5 dB
0000 0000: Left-channel DAC digital gain = 0 dB
1111 1111: Left-channel DAC digital gain = –0.5 dB
...
1000 0010: Left-channel DAC digital gain = –63 dB
1000 0001: Left-channel DAC digital gain = –63.5 dB
1000 0000: Reserved. Do not use.
Page 0 / Register 67: Headset Detection
READ/ RESET
BIT DESCRIPTION
WRITE VALUE
D7 R/W 0 0: Headset detection disabled
1: Headset detection enabled
D6–D5 R XX 00: No headset detected
01: Headset without microphone is detected
10: Reserved
11: Headset with microphone is detected
D4–D2 R/W 000 Debounce Programming for Glitch Rejection During Headset Detection
(1)
000: 16 ms (sampled with 2-ms clock)
001: 32 ms (sampled with 4-ms clock)
010: 64 ms (sampled with 8-ms clock)
011: 128 ms (sampled with 16-ms clock)
100: 256 ms (sampled with 32-ms clock)
101: 512 ms (sampled with 64-ms clock)
110: Reserved
111: Reserved
D1–D0 R/W 00 Debounce Programming for Glitch Rejection During Headset Button-Press Detection
00: 0 ms
01: 8 ms (sampled with 1-ms clock)
10: 16 ms (sampled with 2-ms clock)
11: 32 ms (sampled with 4-ms clock)
(1) Note that these times are generated using the 1 MHz reference clock which is defined in page 3 / register 16.
96 REGISTER MAP Copyright © 2009–2012, Texas Instruments Incorporated
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