Datasheet

TLV320AIC3100
www.ti.com SLAS667A –NOVEMBER 2009–REVISED MAY 2012
Page 0 / Register 62: Programmable Instruction Mode-Control Bits
READ/ RESET
BIT DESCRIPTION
WRITE VALUE
D7 R/W 0 Reserved
D6 R/W 0 ADC PRB engine auxiliary control bit A, which can be used for conditional instructions like JMP
D5 R/W 0 ADC PRB engine auxiliary control bit B, which can be used for conditional instructions like JMP
D4 R/W 0 0: Reset ADC PRB instruction counter at the start of the new frame.
1: Do not reset ADC PRB instruction counter at the start of the new frame.
D3 R/W 0 Reserved
D2 R/W 0 DAC PRB engine auxiliary control bit A, which can be used for conditional instructions like JMP
D1 R/W 0 DAC PRB engine auxiliary control bit B, which can be used for conditional instructions like JMP
D0 R/W 0 0: Reset DAC PRB instruction counter at the start of the new frame.
1: Do not reset DAC PRB instruction counter at the start of the new frame.
Page 0 / Register 63: DAC Data-Path Setup
READ/ RESET
BIT DESCRIPTION
WRITE VALUE
D7 R/W 0 0: Left-channel DAC is powered down.
1: Left-channel DAC is powered up.
D6 R/W 0 0: Right-channel DAC is powered down.
1: Right-channel DAC is powered up.
D5–D4 R/W 01 00: Left-channel DAC data path = off
01: Left-channel DAC data path = left data
10: Left-channel DAC data path = right data
11: Left-channel DAC data path = left-channel and right-channel data [(L + R)/2]
D3–D2 R/W 01 00: Right-channel DAC data path = off
01: Right-channel DAC data path = right data
10: Right-channel DAC data path = left data
11: Right-channel DAC data path = left-channel and right-channel data [(L + R)/2]
D1–D0 R/W 00 00: DAC channel volume control soft-stepping is enabled for one step per sample period.
01: DAC channel volume control soft-stepping is enabled for one step per two sample periods.
10: DAC channel volume control soft-stepping is disabled.
11: Reserved. Do not write this sequence to these bits.
Page 0 / Register 64: DAC VOLUME CONTROL
READ/ RESET
BIT DESCRIPTION
WRITE VALUE
D7–D4 R/W 0000 Reserved. Write only zeros to these bits.
D3 R/W 1 0: Left-channel DAC not muted
1: Left-channel DAC muted
D2 R/W 1 0: Right-channel DAC not muted
1: Right-channel DAC muted
D1–D0
(
R/W 00 00: Left and right channels have independent volume control.
1)
01: Left-channel volume control Is the programmed value of right-channel volume control.
10: Right-channel volume control is the programmed value of left-channel volume control.
11: Same as 00
(1) When DRC is enabled, left- and right-channel volume controls are always independent. Program bits D1–D0 to 00.
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