Datasheet
TLV320AIC3100
SLAS667A –NOVEMBER 2009–REVISED MAY 2012
www.ti.com
Page 0 / Register 39: Overflow Flags
READ/ RESET
BIT DESCRIPTION
WRITE VALUE
D7
(1)
R 0 Left-Channel DAC Overflow Flag
0: Overflow has not occurred.
1: Overflow has occurred.
D6
(1)
R 0 Right-Channel DAC Overflow Flag
0: Overflow has not occurred.
1: Overflow has occurred.
D5
(1)
R 0 DAC Barrel Shifter Output Overflow Flag
0: Overflow has not occurred.
1: Overflow has occurred.
D4 R/W 0 Reserved. Write only zeros to these bits.
D3
(1)
R 0 Delta-Sigma Mono ADC Overflow Flag
0: Overflow has not occurred.
1: Overflow has occurred.
D2 R/W 0 Reserved. Write only zero to this bit.
D1
(1)
R 0 ADC Barrel Shifter Output Overflow Flag
0: Overflow has not occurred.
1: Overflow has occurred.
D0 R/W 0 Reserved. Write only zero to this bit.
(1) Sticky flag bIts. These are read-only bits. They are automatically cleared once they are read and are set only if the source trigger occurs
again.
Page 0 / Registers 40–43: Reserved
READ/ RESET
BIT DESCRIPTION
WRITE VALUE
D7–D0 R/W XXXX XXXX Reserved. Write only the reset value to these bits.
Page 0 / Register 44: Interrupt Flags—DAC
READ/ RESET
BIT DESCRIPTION
WRITE VALUE
D7
(1)
R 0 0: No short circuit is detected at HPL / mono class-D driver.
1: Short circuit is detected at HPL / mono class-D driver.
D6
(1)
R 0 0: Reserved
1: Reserved
D5
(1)
R X 0: No headset button pressed
1: Headset button pressed
D4
(1)
R X 0: No headset insertion/removal is detected.
1: Headset insertion/removal is detected.
D3
(1)
R 0 0: Left DAC signal power is les than or equal to the signal threshold of DRC.
1: Left DAC signal power is above the signal threshold of DRC.
D2
(1)
R 0 0: Right DAC signal power is less than or equal to the signal threshold of DRC.
1: Right DAC signal power is above the signal threshold of DRC.
D1–D0 R 00 Reserved
(1) Sticky flag bIts. These are read-only bits. They are automatically cleared once they are read and are set only if the source trigger occurs
again.
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