Datasheet
TLV320AIC3100
www.ti.com
SLAS667A –NOVEMBER 2009–REVISED MAY 2012
Page 0 / Register 34: I
2
C Bus Condition
READ/ RESET
BIT DESCRIPTION
WRITE VALUE
D7–D6 R/W 00 Reserved. Write only the reset value to these bits.
D5 R/W 0 0: I
2
C general-call address is ignored.
1: Device accepts I
2
C general-call address.
D4–D0 R/W 0 0000 Reserved. Write only zeros to these bits.
Page 0 / Register 35: Reserved
READ/ RESET
BIT DESCRIPTION
WRITE VALUE
D7–D0 R/W XXXX XXXX Reserved. Write only zeros to these bits.
Page 0 / Register 36: ADC Flag Register
READ/ RESET
BIT DESCRIPTION
WRITE VALUE
D7 R 0 0: ADC PGA applied gain ≠ programmed gain
1: ADC PGA applied gain = programmed gain
D6 R 0 0: ADC powered down
1: ADC powered up
D5
(1)
R 0 0: AGC not saturated
1: AGC applied gain = maximum applicable gain by AGC
D4–D0 R/W X XXXX Reserved. Write only zeros to these bits.
(1) Sticky flag bIts. These are read-only bits. They are automatically cleared once they are read and are set only if the source trigger occurs
again.
Page 0 / Register 37: DAC Flag Register
READ/ RESET
BIT DESCRIPTION
WRITE VALUE
D7 R 0 0: Left-channel DAC powered down
1: Left-channel DAC powered up
D6 R/W X Reserved. Write only zero to this bit.
D5 R 0 0: HPl driver powered down
1: HPL driver powered up
D4 R 0 0: Mono class-D driver powered down
1: Mono class-D driver powered up
D3 R 0 0: Right-channel DAC powered down
1: Right-channel DAC powered up
D2 R/W X Reserved. Write only zero to this bit.
D1 R 0 0: HPR driver powered down
1: HPR driver powered up
D0 R 0 0: Reserved
1: Reserved
Page 0 / Register 38: DAC Flag Register
READ/ RESET
BIT DESCRIPTION
WRITE VALUE
D7–D5 R/W XXX Reserved. Do not write to these bits.
D4 R 0 0: Left-channel DAC PGA applied gain ≠ programmed gain
1: Left-channel DAC PGA applied gain = programmed gain
D3–D1 R/W XXX Reserved. Write only zeros to these bits.
D0 R 0 0: Right-channel DAC PGA applied gain ≠ programmed gain
1: Right-channel DAC PGA applied gain = programmed gain
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