Datasheet

TLV320AIC3100
www.ti.com SLAS667A –NOVEMBER 2009–REVISED MAY 2012
Page 0 / Register 15: DAC IDAC_VAL
(1)
READ/ RESET
BIT DESCRIPTION
WRITE VALUE
D7–D0 R/W 1000 0000 0000 0000: Number of instruction for DAC PRB engine, IDAC = 1024
0000 0001: Number of instruction for DAC PRB engine, IDAC = 4
0000 0010: Number of instruction for DAC PRB engine, IDAC = 8
...
1111 1101: Number of instruction for DAC PRB engine, IDAC = 1012
1111 1110: Number of instruction for DAC PRB engine, IDAC = 1016
1111 1111: Number of instruction for DAC PRB engine, IDAC = 1020
(1) IDAC should be an integral multiple of the interpolation in the DAC PRB engine (specified in register 16).
Page 0 / Register 16: DAC PRB Engine Interpolation
READ/ RESET
BIT DESCRIPTION
WRITE VALUE
D7–D4 R/W 0000 Reserved. Do not write to these registers.
D3–D0 R/W 1000 0000: Interpolation ratio in DAC PRB engine = 16
0001: Interpolation ratio in DAC PRB engine = 1
0010: Interpolation ratio in DAC PRB engine = 2
...
1101: Interpolation ratio in DAC PRB engine = 13
1110: Interpolation ratio in DAC PRB engine = 14
1111: Interpolation ratio in DAC PRB engine = 15
Page 0 / Register 17: Reserved
READ/ RESET
BIT DESCRIPTION
WRITE VALUE
D7–D0 R/W XXXX XXXX Reserved. Do not write to this register.
Page 0 / Register 18: ADC NADC_VAL
READ/ RESET
BIT DESCRIPTION
WRITE VALUE
D7 R/W 0 0: ADC NADC divider is powered down and ADC_DSP_CLK = DAC_DSP_CLK.
1: ADC NADC divider is powered up.
D6–D0 R/W 000 0001 000 0000: ADC NADC divider = 128
000 0001: ADC NADC divider = 1
000 0010: ADC NADC divider = 2
...
111 1110: ADC NADC divider = 126
111 1111: ADC NADC divider = 127
Page 0 / Register 19: ADC MADC_VAL
READ/ RESET
BIT DESCRIPTION
WRITE VALUE
D7 R/W 0 0: ADC MADC divider is powered down and ADC_MOD_CLK = DAC_MOD_CLK.
1: ADC MADC divider is powered up.
D6–D0 R/W 000 0001 000 0000: ADC MADC divider = 128
000 0001: ADC MADC divider = 1
000 0010: ADC MADC divider = 2
...
111 1110: ADC MADC divider = 126
111 1111: ADC MADC divider = 127
Page 0 / Register 20: ADC AOSR_VAL
(1)
READ/ RESET
BIT DESCRIPTION
WRITE VALUE
D7–D0 R/W 1000 0000 0000 0000: ADC OSR AOSR divider = 256
0000 0001: ADC OSR AOSR divider = 1
0000 0010: ADC OSR AOSR divider = 2
...
1111 1110: ADC OSR AOSR divider = 254
1111 1111: ADC OSR AOSR divider = 255
(1) ADC OSR should be an integral multiple of the decimation in the ADC PRB engine (specified in register 22).
Copyright © 2009–2012, Texas Instruments Incorporated REGISTER MAP 85
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