Datasheet
TLV320AIC3100
www.ti.com
SLAS667A –NOVEMBER 2009–REVISED MAY 2012
Page 0 / Register 3: OT FLAG
READ/ RESET
BIT DESCRIPTION
WRITE VALUE
D7-D2 R XXXX Reserved. Do not write to these bits.
D1 R 1 0: Overtemperature protection flag (active-low). Valid only if speaker amplifier is powered up
1: Normal operation
D0 R/W XX Reserved. Do not write to these bits.
Page 0 / Register 4: Clock-Gen Muxing
(1)
READ/ RESET
BIT DESCRIPTION
WRITE VALUE
D7–D4 R/W 0000 Reserved. Write only zeros to these bits.
D3–D2 R/W 00 00: PLL_CLKIN = MCLK (device pin)
01: PLL_CLKIN = BCLK (device pin)
10: PLL_CLKIN = GPIO1 (device pin)
11: PLL_CLKIN = DIN (can be used for the system where DAC is not used)
D1–D0 R/W 00 00: CODEC_CLKIN = MCLK (device pin)
01: CODEC_CLKIN = BCLK (device pin)
10: CODEC_CLKIN = GPIO1 (device pin)
11: CODEC_CLKIN = PLL_CLK (generated on-chip)
(1) See for more details on clock generation mutiplexing and dividers.
Page 0 / Register 5: PLL P and R-VAL
READ/ RESET
BIT DESCRIPTION
WRITE VALUE
D7 R/W 0 0: PLL is powered down.
1: PLL is powered up.
D6–D4 R/W 001 000: PLL divider P = 8
001: PLL divider P = 1
010: PLL divider P = 2
...
110: PLL divider P = 6
111: PLL divider P = 7
D3–D0 R/W 0001 0000: PLL multiplier R = 16
0001: PLL multiplier R = 1
0010: PLL multiplier R = 2
...
1110: PLL multiplier R = 14
1111: PLL multiplier R = 15
Page 0 / Register 6: PLL J-VAL
READ/ RESET
BIT DESCRIPTION
WRITE VALUE
D7–D6 R/W 00 Reserved. Write only zeros to these bits.
D5–D0 R/W 00 0100 00 0000: Do not use (reserved)
00 0001: PLL multiplier J = 1
00 0010: PLL multiplier J = 2
...
11 1110: PLL multiplier J = 62
11 1111: PLL multiplier J = 63
Table 6-2. Page 0 / Register 7: PLL D-VAL MSB
(1)
READ/ RESET
BIT DESCRIPTION
WRITE VALUE
D7–D6 R/W 00 Reserved. Write only zeros to these bits.
D5–D0 R/W 00 0000 PLL fractional multiplier D-Val MSB bits D[13:8]
(1) Note that this registeris updated only when page 0 / register 8 is written immediately after page 0 / register 7.
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