Datasheet

LD(n) LD(n+1)
BIT
CLOCK
DATA
N
-
1
N
-
2
N
-
3
2 1 0
3
N
-
1
N
-
2
N
-
3
03 2 1
N
-
1
N
-
2
N
-
3
3
RD(n)
WORD
CLOCK
LEFT CHANNEL RIGHT CHANNEL
LD(n) LD(n+1)
BIT
CLOCK
DATA
-
1
-
2
-
3
2 1 03 -
1
-
2
-
3
03 2 1 -
1
-
2
N N N N N N N N N
-
3
RD(n)
WORD
CLOCK
LEFT CHANNEL RIGHT CHANNEL
LD(n)=n'thsampleofleftchanneldata RD(n)=n'thsampleofrightchanneldata
LD(n) LD (n+1)
BIT
CLOCK
DATA
-
1
-
2
-
3
2 1 03 -
1
-
2
-
3
03 2 1 -
1
-
2
N N N N N N N N N
-
3
3
RD(n)
WORD
CLOCK
LEFT CHANNEL RIGHT CHANNEL
LD(n)=n'thsampleofleftchanneldata RD(n)=n'thsampleofrightchanneldata
TLV320AIC3100
www.ti.com SLAS667A –NOVEMBER 2009–REVISED MAY 2012
5.7.1.4 DSP Mode
The audio interface of the TLV320AIC3100 can be put into DSP mode by programming page 0 /
register 27, bits D7–D6 = 01. In DSP mode, the falling edge of the word clock starts the data transfer with
the left-channel data first and immediately followed by the right-channel data. Each data bit is valid on the
falling edge of the bit clock.
Figure 5-48. Timing Diagram for DSP Mode
Figure 5-49. Timing Diagram for DSP Mode With Offset = 1
Figure 5-50. Timing Diagram for DSP Mode With Offset = 0 and Bit Clock Inverted
For the DSP mode, the number of bit clocks per frame should be greater than or equal to twice the
programmed word length of the data. Also, the programmed offset value should be less than the number
of bit clocks per frame by at least the programmed word length of the data.
Copyright © 2009–2012, Texas Instruments Incorporated APPLICATION INFORMATION 77
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