Datasheet

BCLK
WCLK
T0202-03
DOUT
1
1
0
0
1/f
S
LSB
LSB
LSB
MSB
MSB
MSB
2
2
n–1
n–1
n–2
n–2
n–3
n–3
ADCMonoChannel(D0)
ADCMonoChannel(D0)
1ClockBeforeMSB
1
1
0
0
1/f
S
LSB
MSB
2
2
n–1
n–1
n–1
n–2
n–2
n–3
n–3
ADCMonoChannel(D1)
ADCMonoChannel(D1)
TLV320AIC3100
SLAS667A –NOVEMBER 2009–REVISED MAY 2012 www.ti.com
Figure 5-47. Timing Diagram for I
2
S Mode for Monaural Audio ADC
76 APPLICATION INFORMATION Copyright © 2009–2012, Texas Instruments Incorporated
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