Datasheet

LD(n) LD(n+1)
WORD
CLOCK
BIT
CLOCK
DATA
-
1
-
2
-
3
2 1 03 -
1
-
2
-
3
2 1 03 -
1
-
2
N N N N N N N N N
-
3
3
RD(n)
LEFT CHANNEL RIGHT CHANNEL
LD(n)=n'thsampleofleftchanneldata RD(n)=n'thsampleofrightchanneldata
TLV320AIC3100
www.ti.com SLAS667A –NOVEMBER 2009–REVISED MAY 2012
Figure 5-46. Timing Diagram for I
2
S Mode With Offset = 0 and Bit Clock Inverted
For I
2
S mode, the number of bit clocks per channel should be greater than or equal to the programmed
word length of the data. Also, the programmed offset value should be less than the number of bit clocks
per frame by at least the programmed word length of the data.
Figure 5-47 shows the timing diagram for I
2
S mode for the monoaural audio ADC.
Copyright © 2009–2012, Texas Instruments Incorporated APPLICATION INFORMATION 75
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