Datasheet

LD(n) LD(n+1)
WORD
CLOCK
BIT
CLOCK
DATA
-
1
-
2
-
3
2 1 03 -
1
-
2
-
3
2 1 03 -
1
-
2
N N N N N N N N N
-
3
RD(n)
LEFT CHANNEL RIGHT CHANNEL
LD(n)=n'thsampleofleftchanneldata RD(n)=n'thsampleofrightchanneldata
LD(n) LD(n+1)
WORD
CLOCK
BIT
CLOCK
DATA
-
1
-
2
-
3
2 1 03 -
1
-
2
-
3
2 1 03 -
1
-
2
N N N N N N N N N
-
3
RD(n)
LEFT CHANNEL RIGHT CHANNEL
LD(n)=n'thsampleofleftchanneldata RD(n)=n'thsampleofrightchanneldata
BCLK
WCLK
DIN/DOUT
n-1 n-2 1 00 n-1 n-2 1 0
LSBMSB
LeftChannel RightChannel
n-3 2 2n-3
LSBMSB
1/fs
TLV320AIC3100
www.ti.com SLAS667A –NOVEMBER 2009–REVISED MAY 2012
Figure 5-40. Timing Diagram for Right-Justified Mode
For the right-justified mode, the number of bit clocks per frame should be greater than or equal to twice
the programmed word length of the data.
5.7.1.2 Left-Justified Mode
The audio interface of the TLV320AIC3100 can be put into left-justified mode by programming page 0 /
register 27, bits D7–D6 = 11. In left-justified mode, the MSB of the right channel is valid on the rising edge
of the bit clock following the falling edge of the word clock. Similarly, the MSB of the left channel is valid
on the rising edge of the bit clock following the rising edge of the word clock.
Figure 5-41. Timing Diagram for Left-Justified Mode
Figure 5-42. Timing Diagram for Left-Justified Mode With Offset = 1
Copyright © 2009–2012, Texas Instruments Incorporated APPLICATION INFORMATION 73
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