Datasheet

Internal
Oscillator
÷8
0
1
P3/R16, Bits D6-D0
MCLK
P3/R16, Bit D7
Interval timers
Programmable
Divider
Powered on if
internal oscillator is
selected
Used for de-bounce time for
headset detection logic,
various power up timers and
for generation of interrupts
TLV320AIC3100
www.ti.com SLAS667A –NOVEMBER 2009–REVISED MAY 2012
Table 5-42. PLL Example Configurations
PLL_CLKIN
PLLP PLLR PLLJ PLLD MADC NADC AOSR MDAC NDAC DOSR
(MHz)
f
S
= 44.1 kHz
2.8224 1 3 10 0 3 5 128 3 5 128
5.6448 1 3 5 0 3 5 128 3 5 128
12 1 1 7 560 3 5 128 3 5 128
13 1 1 6 3504 2 9 104 6 3 104
16 1 1 5 2920 3 5 128 3 5 128
19.2 1 1 4 4100 3 5 128 3 5 128
48 4 1 7 560 3 5 128 3 5 128
f
S
= 48 kHz
2.048 1 3 14 0 2 7 128 7 2 128
3.072 1 4 7 0 2 7 128 7 2 128
4.096 1 3 7 0 2 7 128 7 2 128
6.144 1 2 7 0 2 7 128 7 2 128
8.192 1 4 3 0 2 8 128 4 4 128
12 1 1 7 1680 2 7 128 7 2 128
16 1 1 5 3760 2 7 128 7 2 128
19.2 1 1 4 4800 2 7 128 7 2 128
48 4 1 7 1680 2 7 128 7 2 128
5.6.2 Timer
The internal clock runs nominally at 8.2 MHz. This is used for various internal timing intervals, de-bounce
logic, and interrupts. The MCLK divider must be set such a way that the divider output is approximately 1
MHz for the timers to be closer to the programmed value.
Figure 5-39. Interval Timer Clock Selection
Copyright © 2009–2012, Texas Instruments Incorporated APPLICATION INFORMATION 71
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