Datasheet
MHz20
P
CLKIN_PLL
MHz10 ££
MHz20
P
CLKIN_PLL
kHz512 ££
PLL_CLKIN R J.D
PLL_CLK
P
´ ´
=
TLV320AIC3100
SLAS667A –NOVEMBER 2009–REVISED MAY 2012
www.ti.com
5.6.1 PLL
For lower power consumption, it is best to derive the internal audio processing clocks using the simple
dividers. When the input MCLK or other source clock is not an integer multiple of the audio processing
clocks, then it is necessary to use the on-board PLL. The TLV320AIC3100 fractional PLL can be used to
generate an internal master clock used to produce the processing clocks needed by the ADC, DAC, and
processing blocks. The programmability of this PLL allows operation from a wide variety of clocks that
may be available in the system.
The PLL input supports clocks varying from 512 kHz to 20 MHz and is register-programmable to enable
generation of the required sampling rates with fine resolution. The PLL can be turned on by writing to
page 0 / register 5, bit D7. When the PLL is enabled, the PLL output clock, PLL_CLK, is given by the
following equation:
(9)
where
R = 1, 2, 3, ..., 16 (page 0 / register 5, default value = 1)
J = 1, 2, 3, … , 63, (page 0 / register 6, default value = 4)
D = 0, 1, 2, …, 9999 (page 0 / register 7 and page 0 / register 8, default value = 0)
P = 1, 2, 3, …, 8 (page 0 / register 5, default value = 1)
The PLL can be turned on via page 0 / register 5, bit D7. The variable P can be programmed via page 0 /
register 5, bits D6–D4. The variable R can be programmed via page 0 / register 5, bits D3–D0. The
variable J can be programmed via page 0 / register 6, bits D5–D0. The variable D is 14 bits and is
programmed into two registers. The MSB portion can be programmed via page 0 / register 7, bits D5–D0,
and the LSB portion is programmed via page 0 / register 8, bits D7–D0. For proper update of the D divider
value, page 0 / register 7 must be programmed first, followed immediately by page 0 / register 8. Unless
the write to page 0 / register 8 is completed, the new value of D does not take effect.
When the PLL is enabled, the following conditions must be satisfied:
• When the PLL is enabled and D = 0, the following conditions must be satisfied for PLL_CLKIN:
(10)
80 MHz ≤ (PLL_CLKIN × J.D × R/P) ≤ 110 MHz
4 ≤ R × J ≤ 259
• When the PLL is enabled and D ≠ 0, the following conditions must be satisfied for PLL_CLKIN:
(11)
80 MHz ≤ PLL_CLKIN × J.D × R/P ≤ 11 MHz
R = 1
The PLL can be powered up independently from the ADC and DAC blocks, and can also be used as a
general-purpose PLL by routing its output to the GPIO output. After powering up the PLL, PLL_CLK is
available typically after 10 ms.
The clocks for the codec and various signal processing blocks, CODEC_CLKIN, can be generated from
the MCLK input, BCLK input, GPIO input, or PLL_CLK (page 0 / register 4, bits D1–D0).
If CODEC_CLKIN is derived from the PLL, then the PLL must be powered up first and powered down last.
Table 5-42 lists several example cases of typical PLL_CLKIN rates and how to program the PLL to
achieve a sample rate f
S
of either 44.1 kHz or 48 kHz.
70 APPLICATION INFORMATION Copyright © 2009–2012, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): TLV320AIC3100