Datasheet

÷M

CLKOUT

CDIV_CLKIN

MCLK BCLK DIN

PLL_CLK

DAC_CLK ADC_CLK

DAC_MOD_CLK ADC_MOD_CLK

M=1,2,...,127,128

GPIO1

DOUT

TLV320AIC3100

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SLAS667A –NOVEMBER 2009–REVISED MAY 2012

In the mode when the TLV320AIC3100 is configured to drive the BCLK pin (page 0 / register 27,

bit D3 = 1), it can be driven as the divided value of BDIV_CLKIN. The division value can be programmed

from 1 to 128 in page 0 / register 30, bits D6–D0. BDIV_CLKIN can itself be configured to be one of

DAC_CLK (DAC DSP clock), DAC_MOD_CLK, ADC_CLK (ADC DSP clock) or ADC_MOD_CLK by

configuring the BDIV_CLKIN multiplexer in page 0 / register 29, bits D1–D0. Additionally, a general-

purpose clock can be driven out on either GPIO1 or DOUT.

This clock can be a divided-down version of CDIV_CLKIN. The value of this clock divider can be

programmed from 1 to 128 by writing to page 0 / register 26, bits D6–D0. CDIV_CLKIN can itself be

programmed as one of the clocks among the list shown in Figure 5-38. This can be controlled by

programming the multiplexer in page 0 / register 25, bits D2–D0.

Figure 5-38. General-Purpose Clock Output Options

Table 5-41. Maximum TLV320AIC3100 Clock Frequencies

Clock DVDD ≥ 1.65 V

CODEC_CLKIN ≤ 110 MHz

ADC_CLK (ADC DSP clock) ≤ 49.152 MHz

ADC_PRB_CLK ≤ 24.576 MHz

ADC_MOD_CLK 6.758 MHz

ADC_f

0.192 MHz

DAC_CLK (DAC DSP clock) ≤ 49.152 MHz

DAC_PRB_CLK ≤ 49.152 MHz with DRC disabled

≤ 48 MHz with DRC enabled

DAC_MOD_CLK 6.758 MHz

DAC_f

0.192 MHz

BDIV_CLKIN 55 MHz

CDIV_CLKIN 100 MHz when M is odd

110 MHz when M is even

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