Datasheet

S
CODEC _ CLKIN
ADC _ f
NADC MADC AOSR
=
´ ´
S
CODEC _ CLKIN
DAC _ f
NDAC MDAC DOSR
=
´ ´
CODEC _ CLKIN
ADC _ MOD _ CLK
NADC MADC
=
´
CODEC _ CLKIN
DAC _ MOD _ CLK
NDAC MDAC
=
´
PLL
´ ´(R J.D)/P
PLL_CLKIN
CODEC_CLKIN
ADC_CLK
DAC_MOD_CLK
DAC_CLK
ADC_MOD_CLK
NDAC = 1, 2, ..., 127, 128
MDAC = 1, 2, ..., 127, 128
DOSR = 1, 2, ..., 1023, 1024 AOSR = 1, 2, ..., 255, 256
MADC = 1, 2, ..., 127, 128
NADC = 1, 2, ..., 127, 128
MCLK
BCLK
GPIO1
DIN
MCLK
BCLK
GPIO1
PLL_CLK
¸ NADC
¸ MADC¸ MDAC
¸ DOSR ¸ AOSR
¸ NDAC
To DAC_PRB
Clock Generation
To ADC_PRB
Clock Generation
DAC_f
S
ADC_f
S
B0357-05
TLV320AIC3100
www.ti.com SLAS667A –NOVEMBER 2009–REVISED MAY 2012
Figure 5-36. Clock Distribution Tree
(8)
Table 5-40. CODEC CLKIN Clock Dividers
Divider Bits
NDAC Page 0 / register 11, bits D6–D0
MDAC Page 0 / register 12, bits D6–D0
DOSR Page 0 / register 13, bits D1–D0 and page 0 / register 14, bits D7–D0
Copyright © 2009–2012, Texas Instruments Incorporated APPLICATION INFORMATION 67
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