Datasheet

TLV320AIC3100
SLAS667A –NOVEMBER 2009–REVISED MAY 2012 www.ti.com
3.2 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
AVDD
(1)
Referenced to AVSS
(2)
2.7 3.3 3.6
DVDD Referenced to DVSS
(2)
1.65 1.8 1.95
HPVDD Power-supply voltage range Referenced to HPVSS
(2)
2.7 3.3 3.6 V
SPKVDD
(1)
Referenced to SPKVSS
(2)
2.7 5.5
IOVDD Referenced to IOVSS
(2)
1.1 3.3 3.6
Resistance applied across class-D output pins
Speaker impedance 4 Ω
(BTL)
Headphone impedance AC-coupled to R
L
16 Ω
Analog audio full-scale input
V
I
AVDD = 3.3 V, single-ended 0.707 V
RMS
voltage
Stereo line output load
AC-coupled to R
L
10 kΩ
impedance
MCLK
(3)
Master clock frequency IOVDD = 3.3 V 50 MHz
f
SCL
SCL clock frequency 400 kHz
T
A
Operating free-air temperature –40 85 °C
(1) To minimize battery-current leakage, the SPKVDD voltage level should not be below the AVDD voltage level.
(2) All grounds on board are tied together, so they should not differ in voltage by more than 0.2 V maximum for any combination of ground
signals. By use of a wide trace or ground plane, ensure a low-impedance connection between HPVSS and DVSS.
(3) The maximum input frequency should be 50 MHz for any digital pin used as a general-purpose clock.
3.3 Electrical Characteristics
At 25°C, AVDD = HPVDD = IOVDD = 3.3 V, SPKVDD = 3.6 V, DVDD = 1.8 V, f
S
(audio) = 48 kHz, CODEC_CLKIN = 256 ×
f
S
, PLL = Off, VOL/MICDET pin disabled (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
INTERNAL OSCILLATOR—RC_CLK
Oscillator frequency 8.2 MHz
VOLUME CONTROL PIN (ADC); VOL/MICDET PIN ENABLED
VOL/MICDET pin configured as volume control
0.5 ×
Input voltage range (page 0 / register 116, bit D7 = 1 and page 0 / 0 V
AVDD
register 67, bit D7 = 0)
Input capacitance 2 pF
Volume control steps 128 Steps
6 ELECTRICAL SPECIFICATIONS Copyright © 2009–2012, Texas Instruments Incorporated
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