Datasheet

1
st
Order
IIR
AGC
Gain
Compen
sation
AGC
Filter A
H
E
H
D
H
C
H
B
H
A
To Audio
Interface
To AnalogPGA
FromDelta-Sigma
Modulatoror
DigitalMicrophone
From
DigitalVol.Ctrl
´
To Audio
Interface
1
st
Order
IIR
´
AGC
Gain
Compen
Sation
AGC
To AnalogPGA
Filter A
FromDelta-Sigma
Modulatoror
DigitalMicrophone
From
DigitalVol.Ctrl
TLV320AIC3100
SLAS667A –NOVEMBER 2009–REVISED MAY 2012 www.ti.com
Table 5-17. ADC Processing Blocks
Processing Decimation First-Order Number Required Resource
Channel FIR
Blocks Filter IIR Available Biquads AOSR Value Class
PRB_R4 Mono A Yes 0 No 128, 64 3
PRB_R5 Mono A Yes 5 No 128, 64 4
PRB_R6 Mono A Yes 0 25-tap 128, 64 4
PRB_R10 Mono B Yes 0 No 64 2
PRB_R11 Mono B Yes 3 No 64 2
PRB_R12 Mono B Yes 0 20-tap 64 2
PRB_R16 Mono C Yes 0 No 32 2
PRB_R17 Mono C Yes 5 No 32 2
PRB_R18 Mono C Yes 0 25-tap 32 2
5.4.4.2 ADC Processing Blocks – Signal Chain Details
5.4.4.2.1 First-Order IIR, AGC, Filter A
Figure 5-3. Signal Chain for PRB_R4
5.4.4.2.2 Five Biquads, First-Order IIR, AGC, Filter A
Figure 5-4. Signal Chain for PRB_R5
32 APPLICATION INFORMATION Copyright © 2009–2012, Texas Instruments Incorporated
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