Datasheet

TLV320AIC3100
www.ti.com SLAS667A –NOVEMBER 2009–REVISED MAY 2012
5.4 Audio ADC and Analog Inputs
5.4.1 MICBIAS and Microphone Preamplifier
The TLV320AIC3100 includes a microphone bias circuit which can source up to 4 mA of current and is
programmable to a 2-V, 2.5-V, or AVDD level. The level can be controlled by writing to page 1 /
register 46, bits D1–D0. This functionality is shown in Table 5-14.
Table 5-14. MICBIAS Settings
D1 D0 FUNCTIONALITY
0 0 MICBIAS output is powered down.
0 1 MICBIAS output is powered to 2 V.
1 0 MICBIAS output is powered to 2.5 V.
1 1 MICBIAS output is powered to AVDD.
During normal operation, MICBIAS can be set to 2.5 V for better performance. However, depending on the
model of microphone that is selected, optimal performance might be obtained at another setting, so the
performance at a given setting should be verified.
The lowest current consumption occurs when MICBIAS is powered down. The next-lowest current
consumption occurs when MICBIAS is set at AVDD.
Because of the oversampling nature of the audio ADC and the integrated digital decimation filtering,
requirements for analog anti-aliasing filtering are very relaxed. The TLV320AIC3100 integrates a second-
order analog anti-aliasing filter with 20-dB attenuation at 1 MHz. This filter, combined with the digital
decimal filter, provides sufficient anti-aliasing filtering without requiring any external components.
The MIC PGA supports analog gain control from from 0 dB to 59.5 dB in steps of 0.5 dB. These gain
levels can be controlled by writing to page 1 / register 47, bits D6–D0. The PGA gain changes are
implemented with internal soft-stepping. This soft-stepping ensures that volume-control changes occur
smoothly with no audible artifacts. On reset, the MIC PGA gain defaults to a mute condition, with soft-
stepping enabled. The ADC soft-stepping control can be enabled or disabled by writing to page 0 /
register 81, bits D1–D0. ADC soft-stepping timing is provided by the internal oscillator and internal divider
logic block.
The input feed-forward resistance for the MIC1LP input of the microphone PGA stage has three settings,
10 kΩ, 20 kΩ, and 40 kΩ, which are controlled by writing to page 1 / register 48, bits D7 and D6. The input
feed-forward resistance value selected affects the gain of the microphone PGA. The ADC PGA gain for
the MIC1LP input depends on the setting of page 1 / register 48 and page 1 / register 49, bits D7–D6. If
D7–D6 are set to 01, then the ADC PGA has 6 dB more gain with respect to the value programmed using
page 1 / register 47. If D7–D6 are set to 10, then the ADC PGA has the same gain as programmed using
page 1 / register 47. If D7–D6 are set to 11, then the ADC PGA has 6 dB less gain with respect to the
value programmed using page 1 / register 47. The same gain scaling is also valid for the MIC1RP and
MIC1LM inputs, based on the feed-forward resistance selected using page 1 / register 48, bits D5–D2.
Table 5-15. PGA Gain Versus Input Impedance
EFFECTIVE GAIN APPLIED BY PGA
Page 1 Reg 47
Single-Ended Differential
D6–D0
RIN = 10 kΩ RIN = 20 kΩ RIN = 40 kΩ RIN = 10 kΩ RIN = 20 kΩ RIN = 40 kΩ
000 0000 6 dB 0 dB –6 dB 12 dB 6 dB 0 dB
000 0001 6.5 dB 0.5 dB –5.5 dB 12.5 dB 6.5 dB 0.5 dB
000 0010 7 dB 1 dB –5 dB 13 dB 7 dB 1 dB
... ... ... ... ... ... ...
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