Datasheet

TLV320AIC3100
www.ti.com SLAS667A –NOVEMBER 2009–REVISED MAY 2012
Table 6-5. Page-4 Registers (continued)
REGISTER
RESET VALUE REGISTER NAME
NUMBER
47 0000 0000 Coefficient N1(7:0) for ADC biquad D or coefficient FIR16(7:0) for ADC FIR filter
48 0000 0000 Coefficient N2(15:8) for ADC biquad D or coefficient FIR17(15:8) for ADC FIR filter
49 0000 0000 Coefficient N2(7:0) for ADC biquad D or coefficient FIR17(7:0) for ADC FIR filter
50 0000 0000 Coefficient D1(15:8) for ADC biquad D or coefficient FIR18(15:8) for ADC FIR filter
51 0000 0000 Coefficient D1(7:0) for ADC biquad D or coefficient FIR18(7:0) for ADC FIR filter
52 0000 0000 Coefficient D2(15:8) for ADC biquad D or coefficient FIR19(15:8) for ADC FIR filter
53 0000 0000 Coefficient D2(7:0) for ADC biquad D or coefficient FIR19(7:0) for ADC FIR filter
54 0111 1111 Coefficient N0(15:8) for ADC biquad E or coefficient FIR20(15:8) for ADC FIR filter
55 1111 1111 Coefficient N0(7:0) for ADC biquad E or coefficient FIR20(7:0) for ADC FIR filter
56 0000 0000 Coefficient N1(15:8) for ADC biquad E or coefficient FIR21(15:8) for ADC FIR filter
57 0000 0000 Coefficient N1(7:0) for ADC biquad E or coefficient FIR21(7:0) for ADC FIR filter
58 0000 0000 Coefficient N2(15:8) for ADC biquad E or coefficient FIR22(15:8) for ADC FIR filter
59 0000 0000 Coefficient N2(7:0) for ADC biquad E or coefficient FIR22(7:0) for ADC FIR filter
60 0000 0000 Coefficient D1(15:8) for ADC biquad E or coefficient FIR23(15:8) for ADC FIR filter
61 0000 0000 Coefficient D1(7:0) for ADC biquad E or coefficient FIR23(7:0) for ADC FIR filter
62 0000 0000 Coefficient D2(15:8) for ADC biquad E or coefficient FIR24(15:8) for ADC FIR filter
63 0000 0000 Coefficient D2(7:0) for ADC biquad E or coefficient FIR24(7:0) for ADC FIR filter
64-127 0000 0000 Reserved. Write only reset values.
6.6 Control Registers, Page 8: DAC Digital Filter Coefficients
Default values shown for this page only become valid 100 μs following a hardware or software reset.
Page 8 / Register 0: Page Control Register
READ/ RESET
BIT DESCRIPTION
WRITE VALUE
D7–D0 R/W 0000 0000 0000 0000: Page 0 selected
0000 0001: Page 1 selected
...
1111 1110: Page 254 selected
1111 1111: Page 255 selected
Page 8 / Register 1: DAC Coefficient Buffer Control
READ/ RESET
BIT DESCRIPTION
WRITE VALUE
D7–D4 R/W 0000 Reserved. Write only the reset value.
D3 R 0 DAC PRB-generated flag for toggling MSB of coefficient RAM address (only used in non-adaptive mode)
D2 R/W 0 DAC Adaptive Filtering Control
0: Adaptive filtering disabled in DAC processing blocks
1: Adaptive filtering enabled in DAC processing blocks
D1 R 0 DAC Adaptive Filter Buffer Control Flag
0: In adaptive filter mode, DAC processing blocks accesses DAC coefficient buffer A and the external
control interface accesses DAC coefficient buffer B
1: In adaptive filter mode, DAC processing blocks accesses DAC coefficient buffer B and the external
control interface accesses DAC coefficient buffer A
D0 R/W 0 DAC Adaptive Filter Buffer Switch Control
0: DAC coefficient buffers are not switched at the next frame boundary
1: DAC coefficient buffers are switched at the next frame boundary, if adaptive filtering mode is enabled.
This bit self-clears on switching.
Copyright © 2009–2012, Texas Instruments Incorporated REGISTER MAP 113
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