Datasheet

TLV320AIC3100
www.ti.com SLAS667A –NOVEMBER 2009–REVISED MAY 2012
Page 1 / Registers 51–127: Reserved
READ/ RESET
BIT DESCRIPTION
WRITE VALUE
D7–D0 R/W XXXX XXXX Reserved. Write only the reset value to these bits.
6.4 Control Registers, Page 3: MCLK Divider for Programmable Delay Timer
Default values shown for this page only become valid 100 μs following a hardware or software reset.
Table 6-3. Page 3 / Register 0: Page Control Register
READ/ RESET
BIT DESCRIPTION
WRITE VALUE
D7–D0 R/W 0000 0000 0000 0000: Page 0 selected
0000 0001: Page 1 selected
...
1111 1110: Page 254 selected
1111 1111: Page 255 selected
The only register used in page 3 is register 16. The remaining page 3 registers are reserved and should
not be written to.
Table 6-4. Page 3 / Register 16: Timer Clock MCLK Divider
READ/ RESET
BIT DESCRIPTION
WRITE VALUE
D7 R/W 1 0: Internal oscillator is used for programmable delay timer.
1: External MCLK
(1)
is used for programmable delay timer.
D6–D0 R/W 000 0001 MCLK Divider to Generate 1-MHz Clock for the Programmable Delay Timer
000 0000: MCLK divider = 128
000 0001: MCLK divider = 1
000 0010: MCLK divider = 2
...
111 1110: MCLK divider = 126
111 1111: MCLK divider = 127
(1) External clock is used only to control the delay programmed between the conversions and not used for doing the actual conversion. This
feature is provided in case a more accurate delay is desired since the internal oscillator frequency varies from device to device.
6.5 Control Registers, Page 4: ADC Digital Filter Coefficients
Default values shown for this page only become valid 100 μs following a hardware or software reset.
Page 4 / Register 0: Page Control Register
READ/ RESET
BIT DESCRIPTION
WRITE VALUE
D7–D0 R/W 0000 0000 0000 0000: Page 0 selected
0000 0001: Page 1 selected
...
1111 1110: Page 254 selected
1111 1111: Page 255 selected
The remaining page-4 registers are either reserved registers or are used for setting coefficients for the
various filters in the TLV320AIC3100. Reserved registers should not be written to.
The filter coefficient registers are arranged in pairs, with two adjacent 8-bit registers containing the 16-bit
coefficient for a single filter. The 16-bit integer contained in the MSB and LSB registers for a coefficient
are interpreted as a 2s-complement integer, with possible values ranging from –32,768 to 32,767. When
programming any coefficient value for a filter, the MSB register should always be written first, immediately
followed by the LSB register. Even if only the MSB or LSB portion of the coefficient changes, both
registers should be written in this sequence. Table 6-5 is a list of the page 4 registers, excepting the
previously described register 0.
Copyright © 2009–2012, Texas Instruments Incorporated REGISTER MAP 111
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