Datasheet

T0145-09
WCLK
BCLK
DOUT
DIN
t (WS)
h
t (BCLK)
H
t (DO-BCLK)
d
t (DO-WS)
d
t (DI)
S
t (BCLK)
L
t (DI)
h
t (WS)
S
t
r
t
f
TLV320AIC3100
www.ti.com SLAS667A –NOVEMBER 2009–REVISED MAY 2012
3.4.2 I
2
S/LJF/RJF Timing in Slave Mode
All specifications at 25°C, DVDD = 1.8 V
Note: All timing specifications are measured at characterization but not tested at final test.
IOVDD = 1.1 V IOVDD = 3.3 V
PARAMETER UNIT
MIN MAX MIN MAX
t
H
(BCLK) BCLK high period 35 35 ns
t
L
(BCLK) BCLK low period 35 35 ns
t
s
(WS) WCLK setup 8 6 ns
t
h
(WS) WCLK hold 8 6 ns
t
d
(DO-WS) WCLK to DOUT delay (for LJF mode only) 45 20 ns
t
d
(DO-BCLK) BCLK to DOUT delay 45 20 ns
t
s
(DI) DIN setup 8 6 ns
t
h
(DI) DIN hold 8 6 ns
t
r
Rise time 4 4 ns
t
f
Fall time 4 4 ns
Figure 3-2. I
2
S/LJF/RJF Timing in Slave Mode
Copyright © 2009–2012, Texas Instruments Incorporated ELECTRICAL SPECIFICATIONS 11
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