Datasheet

T0145-08
WCLK
BCLK
DOUT
DIN
t (DO-BCLK)
d
t (DO-WS)
d
t (WS)
d
t (DI)
S
t (DI)
h
t
r
t
f
TLV320AIC3100
SLAS667A –NOVEMBER 2009–REVISED MAY 2012 www.ti.com
3.4 Timing Characteristics
3.4.1 I
2
S/LJF/RJF Timing in Master Mode
All specifications at 25°C, DVDD = 1.8 V
Note: All timing specifications are measured at characterization but not tested at final test.
IOVDD = 1.1 V IOVDD = 3.3 V
PARAMETER UNIT
MIN MAX MIN MAX
t
d
(WS) WCLK delay 45 20 ns
t
d
(DO-WS) WCLK to DOUT delay (for LJF mode only) 45 20 ns
t
d
(DO-BCLK) BCLK to DOUT delay 45 20 ns
t
s
(DI) DIN setup 8 6 ns
t
h
(DI) DIN hold 8 6 ns
t
r
Rise time 25 10 ns
t
f
Fall time 25 10 ns
Figure 3-1. I
2
S/LJF/RJF Timing in Master Mode
10 ELECTRICAL SPECIFICATIONS Copyright © 2009–2012, Texas Instruments Incorporated
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