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TLV320AIC3100

www.ti.com

SLAS667A –NOVEMBER 2009–REVISED MAY 2012

Low-Power Audio Codec With Audio Processing and Mono Class-

D Amplifier

Check for Samples: TLV320AIC3100

1 INTRODUCTION

1.1 Features 1.2 Applications

123

• Stereo Audio DAC With 95-dB SNR

• Portable Audio Devices

• Mono Audio ADC With 91-dB SNR

• Mobile Internet Devices

• Supports 8-kHz to 192-kHz Separate DAC and

• Adaptive Filtering Applications

ADC Sample Rates

• Mono Class-D BTL Speaker Driver (2.5 W Into

1.3 Description

4 Ω or 1.6 W Into 8 Ω)

• One Differential and Three Single-Ended Inputs

The TLV320AIC3100 is a low-power, highly

With Mixing and Level Control

integrated, high-performance codec which provides a

• Microphone With Bias, Preamp PGA, and AGC

stereo audio DAC, a mono audio ADC, and a mono

• Built-In Digital Audio Processing Blocks (PRB) class-D 4-Ω speaker driver.

With User-Programmable Biquad and FIR

The TLV320AIC3100 features a high-performance

Filters

audio codec with 24-bit stereo playback and

• Digital Mixing Capability

monaural record functionality. The device integrates

• Programmable Digital Audio Processor for

several analog features, such as a microphone

Bass Boost/Treble/EQ With up to Five Biquads

interface, headphone drivers, and speaker drivers.

for Record and up to Six Biquads for Playback

The TLV320AIC3100 has built-in digital audio

• Pin Control or Register Control for Digital-

processing blocks (PRB) for both the DAC and ADC

Playback Volume-Control Settings

paths. The digital audio data format is programmable

• Digital Sine-Wave Generator for Beep

to work with popular audio standard protocols (I

• Integrated PLL Used for Programmable Digital

left/right-justified) in master, slave, DSP, and TDM

Audio Processor

modes. Bass boost, treble, or EQ can be supported

• I

S, Left-Justified, Right-Justified, DSP, and

by the programmable digital signal-processing block.

TDM Audio Interfaces

An on-chip PLL provides the high-speed clock

• I

C Control With Register Auto-Increment

needed by the digital signal-processing block. The

• Full Power-Down Control

volume level can be controlled by either pin control or

• Power Supplies:

by register control. The audio functions are controlled

– Analog: 2.7 V–3.6 V

using the I

C serial bus.

– Digital Core: 1.65 V–1.95 V

The TLV320AIC3100 has a programmable digital

– Digital I/O: 1.1 V–3.6 V

sine-wave generator and is available in a 32-pin QFN

– Class-D: 2.7 V–5.5 V (SPKVDD ≥ AVDD)

package.

• 5-mm × 5-mm 32-QFN Package

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2MATLAB is a trademark of The MathWorks, Inc.

3All other trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date. Products conform to

specifications per the terms of the Texas Instruments standard warranty. Production

processing does not necessarily include testing of all parameters.

Summary of content (129 pages)

PAGE 1
TLV320AIC3100 www.ti.com SLAS667A – NOVEMBER 2009 – REVISED MAY 2012 Low-Power Audio Codec With Audio Processing and Mono ClassD Amplifier Check for Samples: TLV320AIC3100 1 INTRODUCTION 1.1 Features • Stereo Audio DAC With 95-dB SNR • Mono Audio ADC With 91-dB SNR • Supports 8-kHz to 192-kHz Separate DAC and ADC Sample Rates • Mono Class-D BTL Speaker Driver (2.5 W Into 4 Ω or 1.
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TLV320AIC3100 SLAS667A – NOVEMBER 2009 – REVISED MAY 2012 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure.
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TLV320AIC3100 www.ti.com SLAS667A – NOVEMBER 2009 – REVISED MAY 2012 NOTE This data manual is designed using PDF document-viewing features that allow quick access to information. For example, performing a global search on "page 0 / register 27" produces all references to this page and register in a list. This makes it easy to traverse the list and find all information related to a page and register. Note that the search string must be of the indicated format.
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TLV320AIC3100 SLAS667A – NOVEMBER 2009 – REVISED MAY 2012 www.ti.com 2 PACKAGE AND SIGNAL DESCRIPTIONS 2.1 Package/Ordering Information PRODUCT PACKAGE PACKAGE DESIGNATOR OPERATING TEMPERATURE RANGE TLV320AIC3100 QFN-32 RHB –40°C to 85°C 2.
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TLV320AIC3100 www.ti.com SLAS667A – NOVEMBER 2009 – REVISED MAY 2012 Table 2-1. TERMINAL FUNCTIONS (continued) TERMINAL NAME NO.
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TLV320AIC3100 SLAS667A – NOVEMBER 2009 – REVISED MAY 2012 3.2 www.ti.com Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN NOM (2) 2.7 3.3 3.6 Referenced to DVSS(2) 1.65 1.8 1.95 Referenced to HPVSS(2) 2.7 3.3 3.6 SPKVDD (1) Referenced to SPKVSS(2) 2.7 IOVDD Referenced to IOVSS(2) 1.1 AVDD (1) Referenced to AVSS DVDD HPVDD VI MCLK fSCL TA (1) (2) (3) 3.
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TLV320AIC3100 www.ti.com SLAS667A – NOVEMBER 2009 – REVISED MAY 2012 Electrical Characteristics (continued) At 25°C, AVDD = HPVDD = IOVDD = 3.3 V, SPKVDD = 3.6 V, DVDD = 1.
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TLV320AIC3100 SLAS667A – NOVEMBER 2009 – REVISED MAY 2012 www.ti.com Electrical Characteristics (continued) At 25°C, AVDD = HPVDD = IOVDD = 3.3 V, SPKVDD = 3.6 V, DVDD = 1.8 V, fS (audio) = 48 kHz, CODEC_CLKIN = 256 × fS, PLL = Off, VOL/MICDET pin disabled (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DAC Output to Class-D Speaker Output; Load = 4 Ω (Differential), 50 pF SPKVDD 3.6 V, BTL measurement, CM = 1.8 V, DAC input = 0 dBFS, class-D gain = 6 dB, THD ≤ –16.5 dB 2.
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TLV320AIC3100 www.ti.com SLAS667A – NOVEMBER 2009 – REVISED MAY 2012 Electrical Characteristics (continued) At 25°C, AVDD = HPVDD = IOVDD = 3.3 V, SPKVDD = 3.6 V, DVDD = 1.8 V, fS (audio) = 48 kHz, CODEC_CLKIN = 256 × fS, PLL = Off, VOL/MICDET pin disabled (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DAC POWER CONSUMPTION DAC power consumption is based on selected processing block, see Section 5.3.
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TLV320AIC3100 SLAS667A – NOVEMBER 2009 – REVISED MAY 2012 3.4 3.4.1 www.ti.com Timing Characteristics I2S/LJF/RJF Timing in Master Mode All specifications at 25°C, DVDD = 1.8 V Note: All timing specifications are measured at characterization but not tested at final test.
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TLV320AIC3100 www.ti.com 3.4.2 SLAS667A – NOVEMBER 2009 – REVISED MAY 2012 I2S/LJF/RJF Timing in Slave Mode All specifications at 25°C, DVDD = 1.8 V Note: All timing specifications are measured at characterization but not tested at final test.
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TLV320AIC3100 SLAS667A – NOVEMBER 2009 – REVISED MAY 2012 3.4.3 www.ti.com DSP Timing in Master Mode All specifications at 25°C, DVDD = 1.8 V Note: All timing specifications are measured at characterization but not tested at final test. WCLK td(WS) td(WS) tf BCLK tr td(DO-BCLK) DOUT tS(DI) th(DI) DIN T0146-07 PARAMETER td(WS) td(DO-BCLK) ts(DI) th(DI) tr tf WCLK delay BCLK to DOUT delay DIN setup DIN hold Rise time Fall time IOVDD = 1.1 V MIN MAX 45 45 8 8 25 25 IOVDD = 3.
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TLV320AIC3100 www.ti.com 3.4.4 SLAS667A – NOVEMBER 2009 – REVISED MAY 2012 DSP Timing in Slave Mode All specifications at 25°C, DVDD = 1.8 V Note: All timing specifications are measured at characterization but not tested at final test.
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TLV320AIC3100 SLAS667A – NOVEMBER 2009 – REVISED MAY 2012 3.4.5 www.ti.com I2C Interface Timing All specifications at 25°C, DVDD = 1.8 V Note: All timing specifications are measured at characterization but not tested at final test. SDA tBUF tLOW tr tHIGH tf tHD;STA SCL tHD;STA tSU;DAT tHD;DAT STO tSU;STO tSU;STA STA STA STO T0295-02 PARAMETER fSCL tHD;STA tLOW tHIGH tSU;STA tHD;DAT tSU;DAT tr tf tSU;STO tBUF Cb SCL clock frequency Hold time (repeated) START condition.
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TLV320AIC3100 www.ti.com SLAS667A – NOVEMBER 2009 – REVISED MAY 2012 4 TYPICAL PERFORMANCE 4.1 Audio ADC Performance Added Text for Spacing AMPLITUDE vs FREQUENCY AMPLITUDE vs FREQUENCY 20 20 AVDD = HPVDD = 3.3 V IOVDD = SPKVDD = 3.3 V DVDD = 1.8 V AVDD = HPVDD = 3.3 V IOVDD = SPKVDD = 3.3 V DVDD = 1.
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TLV320AIC3100 SLAS667A – NOVEMBER 2009 – REVISED MAY 2012 www.ti.com AMPLITUDE vs FREQUENCY SNR vs PGA CHANNEL GAIN 0 100 AVDD = HPVDD = 3.3 V IOVDD = SPKVDD = 3.3 V DVDD = 1.8 V −10 Diff = 10k 90 −30 85 −40 80 SNR − dB Amplitude − dBFS −20 95 −50 −60 SE = 10k 70 65 −80 60 −90 55 0 50 100 150 Diff = 40k 75 −70 −100 Diff = 20k SE = 20k SE = 40k 50 −10 200 0 10 f − Frequency − kHz G005 40 50 60 70 80 G006 Figure 4-6.
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TLV320AIC3100 www.ti.com SLAS667A – NOVEMBER 2009 – REVISED MAY 2012 TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT POWER THD+N − Total Harmonic Distortion + Noise − dB 0 HPVDD = 2.7 V CM = 1.35 V −10 −20 −30 −40 HPVDD = 3 V CM = 1.5 V −50 HPVDD = 3.3 V CM = 1.65 V −60 HPVDD = 3.6 V CM = 1.8 V −70 IOVDD = 3.3 V DVDD = 1.8 V Driver Gain = 9 dB RL = 16 Ω −80 −90 −100 0.00 0.02 0.04 0.06 0.08 0.10 0.12 PO − Output Power − W 0.14 G009 Figure 4-9. Headphone Output Power 4.
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TLV320AIC3100 SLAS667A – NOVEMBER 2009 – REVISED MAY 2012 www.ti.com TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT POWER TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT POWER 0 AVDD = HPVDD = 3.3 V IOVDD = 3.3 V SPKVDD = 5.5 V DVDD = 1.8 V RL = 8 Ω −10 −20 THD+N − Total Harmonic Distortion + Noise − dB THD+N − Total Harmonic Distortion + Noise − dB 0 Driver Gain = 18 dB −30 Driver Gain = 24 dB −40 Driver Gain = 12 dB −50 Driver Gain = 6 dB −60 −70 0.0 0.5 1.0 1.5 2.
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TLV320AIC3100 www.ti.com 4.5 SLAS667A – NOVEMBER 2009 – REVISED MAY 2012 MICBIAS Performance Added Text for Spacing VOLTAGE vs CURRENT 3.5 3.0 Micbias = AVDD (3.3 V) V − Voltage − V 2.5 Micbias = 2.5 V 2.0 Micbias = 2 V 1.5 1.0 0.5 0.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 I − Current − mA G016 Figure 4-16.
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TLV320AIC3100 SLAS667A – NOVEMBER 2009 – REVISED MAY 2012 www.ti.com 5 APPLICATION INFORMATION Typical Circuit Configuration +3.3VA SVDD 0.1 mF 22 mF 0.1 mF SPKVDD SPKVDD 4W 22 mF 0.1 mF SPKVSS SPKVSS 0.1 mF 10 mF HPVDD AVDD SPKP SPKP SPKM SPKM 10 mF AVSS HPVSS GPIO1 SDA VOL/MICDET SCL 2.2 kW MICBIAS 0.1 mF MCLK MIC1RP 47 mF HPLOUT Headset DOUT 47 mF WCLK HPROUT HOST PROCESSOR 5.1 DIN BCLK 1 mF Analog_In1 MIC1LP RESET 1 mF Analog_In2 MIC1LM DVDD DVSS +1.8VD 0.
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TLV320AIC3100 www.ti.com • • • • • • • SLAS667A – NOVEMBER 2009 – REVISED MAY 2012 Stereo headphone/lineout amplifier Class-D mono amplifier able to drive a 4-Ω speaker Pin-controlled or register-controlled volume level Power-down de-pop and power-up soft start Analog inputs I2C control interface Power-down control block Following a toggle of the RESET pin or a software reset, the device operates in the default mode. The I2C interface is used to write to the control registers to configure the device.
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TLV320AIC3100 SLAS667A – NOVEMBER 2009 – REVISED MAY 2012 5.2.2 www.ti.com Audio Analog I/O The TLV320AIC3100 has a stereo audio DAC and a monaural ADC. It supports a wide range of analog interfaces to support different headsets and analog outputs. The TLV320AIC3100 has features to interface output drivers (8-Ω, 16-Ω, 32-Ω) and a microphone PGA with AGC control. A special circuit has also been included in the TLV320AIC3100 to insert a short key-click sound into the stereo audio output.
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TLV320AIC3100 www.ti.com 5.3.1 SLAS667A – NOVEMBER 2009 – REVISED MAY 2012 ADC, Mono, 48 kHz, DVDD = 1.8 V, AVDD = 3.3 V AOSR = 128, Processing Block = PRB_R4 (Decimation Filter A) Power consumption = 9.01 mW Table 5-1. PRB_R4 Alternative Processing Blocks, 9.01 mW Processing Block Filter Estimated Power Change (mW) PRB_R5 A 0.23 PRB_R6 A 0.22 AOSR = 64, Processing Block = PRB_R11 (Decimation Filter B) Power consumption = 7.99 mW Table 5-2. PRB_R11 Alternative Processing Blocks, 7.99 mW 5.3.
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TLV320AIC3100 SLAS667A – NOVEMBER 2009 – REVISED MAY 2012 5.3.3 www.ti.com DAC Playback on Headphones, Stereo, 48 kHz, DVDD = 1.8 V, AVDD = 3.3 V, HPVDD = 3.3 V DOSR = 128, Processing Block = PRB_P7 (Interpolation Filter B) Power consumption = 24.28 mW Table 5-5. PRB_P7 Alternative Processing Blocks, 24.28 mW Processing Block Filter Estimated Power Change (mW) PRB_P1 A 1.34 PRB_P2 A 2.86 PRB_P3 A 2.11 PRB_P8 B 1.18 PRB_P9 B 0.53 PRB_P10 B 1.89 PRB_P11 B 0.87 PRB_P23 A 1.
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TLV320AIC3100 www.ti.com SLAS667A – NOVEMBER 2009 – REVISED MAY 2012 DOSR = 64, Processing Block = PRB_P12 (Interpolation Filter B) Power consumption = 15.54 mW Table 5-8. PRB_P12 Alternative Processing Blocks, 15.54 mW 5.3.5 Processing Block Filter Estimated Power Change (mW) PRB_P4 A 0.37 PRB_P5 A 1.23 PRB_P6 A 1.15 PRB_P13 B 0.43 PRB_P14 B 0.13 PRB_P15 B 0.85 PRB_P16 B 0.21 DAC Playback on Headphones, Stereo, 8 kHz, DVDD = 1.8 V, AVDD = 3.3 V, HPVDD = 3.
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TLV320AIC3100 SLAS667A – NOVEMBER 2009 – REVISED MAY 2012 5.3.6 www.ti.com DAC Playback on Headphones, Mono, 8 kHz, DVDD = 1.8 V, AVDD = 3.3 V, HPVDD = 3.3 V DOSR = 768, Processing Block = PRB_P12 (Interpolation Filter B) Power consumption = 14.49 mW Table 5-11. PRB_P12 Alternative Processing Blocks, 14.49 mW Processing Block Filter Estimated Power Change (mW) PRB_P4 A –0.04 PRB_P5 A 0.2 PRB_P6 A –0.01 PRB_P13 B 0.1 PRB_P14 B 0.05 PRB_P15 B –0.03 PRB_P16 B 0.
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TLV320AIC3100 www.ti.com 5.4 SLAS667A – NOVEMBER 2009 – REVISED MAY 2012 Audio ADC and Analog Inputs 5.4.1 MICBIAS and Microphone Preamplifier The TLV320AIC3100 includes a microphone bias circuit which can source up to 4 mA of current and is programmable to a 2-V, 2.5-V, or AVDD level. The level can be controlled by writing to page 1 / register 46, bits D1–D0. This functionality is shown in Table 5-14. Table 5-14. MICBIAS Settings D1 D0 0 0 MICBIAS output is powered down.
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TLV320AIC3100 SLAS667A – NOVEMBER 2009 – REVISED MAY 2012 www.ti.com The MIC PGA gain can be controlled either by an AGC loop or as a fixed gain. See Figure 1-1 for the various analog input routings to the MIC PGA that are supported in the single-ended and differential configurations. The AGC can be enabled by writing to page 0 / register 86, bit D7. If the AGC is not enabled, then setting a fixed gain is done by writing to page 1 / register 47, bits D6–D0.
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TLV320AIC3100 www.ti.com SLAS667A – NOVEMBER 2009 – REVISED MAY 2012 Max PGA applicable allows the user to restrict the maximum gain applied by the AGC. This can be used for limiting PGA gain in situations where environmental noise is greater than the programmed noise threshold. Microphone input maximum PGA can be programmed from 0 dB to 59.5 dB in steps of 0.5 dB. Programming the maximum PGA gain allowed by the AGC is done by writing to page 0 / register 88, bits D6–D0.
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TLV320AIC3100 SLAS667A – NOVEMBER 2009 – REVISED MAY 2012 www.ti.com Table 5-16.
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TLV320AIC3100 www.ti.com SLAS667A – NOVEMBER 2009 – REVISED MAY 2012 One example of AGC code follows, but actual use of code should be verified based on application usage. Note that the AGC code should be set up before powering up the ADC.
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TLV320AIC3100 SLAS667A – NOVEMBER 2009 – REVISED MAY 2012 www.ti.com Table 5-17.
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TLV320AIC3100 www.ti.com SLAS667A – NOVEMBER 2009 – REVISED MAY 2012 5.4.4.2.3 25-Tap FIR, First-Order IIR, AGC, Filter A From Delta-Sigma Modulator or Digital Microphone AGC Gain Compen sation st Filter A 1 Order IIR ´ 25-Tap FIR To Audio Interface AGC From Digital Vol. Ctrl To Analog PGA Figure 5-5. Signal Chain for PRB_R6 5.4.4.2.
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TLV320AIC3100 SLAS667A – NOVEMBER 2009 – REVISED MAY 2012 www.ti.com 5.4.4.2.7 First-Order IIR, AGC, Filter C From Delta-Sigma Modulator or Digital Microphone ´ Filter C AGC Gain Compen sation st 1 Order IIR To Audio Interface AGC From Digital Vol. Ctrl To Analog PGA Figure 5-9. Signal Chain for PRB_R16 5.4.4.2.
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TLV320AIC3100 www.ti.com SLAS667A – NOVEMBER 2009 – REVISED MAY 2012 The coefficients of these filters are each 16 bits wide, in 2s-complement format, and occupy two consecutive 8-bit registers in the register space. Specifically, the filter coefficients are in 1.15 (one dot 15) format with a range from –1.0 (0x8000) to 0.999969482421875 (0x7FFF), as shown in Figure 5-12. 2 –15 2 2 –4 –1 Bit Bit Largest Positive Number: = 0.111111111111111111 = 0.999969482421875 = 1.
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TLV320AIC3100 SLAS667A – NOVEMBER 2009 – REVISED MAY 2012 www.ti.com Table 5-19. ADC Biquad Filter Coefficients (continued) Filter Filter Coefficient Biquad C N0 Page 4 / register 34 and page 4 / register 35 0x7FFF (decimal 1.
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TLV320AIC3100 www.ti.com SLAS667A – NOVEMBER 2009 – REVISED MAY 2012 Table 5-20.
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TLV320AIC3100 SLAS667A – NOVEMBER 2009 – REVISED MAY 2012 www.ti.com 5.4.4.4.1 Decimation Filter A This filter is intended for use at sampling rates up to 48 kHz. When configuring this filter, the oversampling ratio of the ADC can either be 128 or 64. For highest performance, the oversampling ratio must be set to 128. Filter A can also be used for 96 kHz at an AOSR of 64. Table 5-21. ADC Decimation-Filter-A Specifications Parameter Condition Value (Typical) Unit AOSR = 128 Filter gain pass band 0…0.
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TLV320AIC3100 www.ti.com SLAS667A – NOVEMBER 2009 – REVISED MAY 2012 5.4.4.4.2 Decimation Filter B Filter B is intended to support sampling rates up to 96 kHz at an oversampling ratio of 64. Table 5-22. ADC Decimation-Filter-B Specifications Parameter Condition Value (Typical) Unit AOSR = 64 Filter gain pass band 0…0.39 fS ±0.077 dB Filter gain stop band 0.60 fS…32 fS –46 dB Filter group delay 11/fS s Pass-band ripple, 8 ksps 0…0.39 fS 0.076 dB Pass-band ripple, 44.1 ksps 0…0.39 fS 0.
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TLV320AIC3100 SLAS667A – NOVEMBER 2009 – REVISED MAY 2012 www.ti.com 5.4.4.4.3 Decimation Filter C Filter C along with an AOSR of 32 is specially designed for 192-ksps operation for the ADC. The pass band, which extends up to 0.11 × fS (corresponding to 21 kHz), is suited for audio applications. Table 5-23. ADC Decimation-Filter-C Specifications Parameter Condition Value (Typical) Unit Filter gain from 0 to 0.11 fS 0…0.11 fS ±0.033 dB Filter gain from 0.28 fS to 16 fS 0.
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TLV320AIC3100 www.ti.com SLAS667A – NOVEMBER 2009 – REVISED MAY 2012 Record - Paused Volume Ramp Down Soft Mute ADC Volume Ramp Down WAIT Time (A) Wait (A) ms For fS = 32 kHz ® Wait 10 ms (min) For fS = 48 kHz ® Wait 8 ms (min) ADC Power Down Update Digital Filter Coefficients ADC Volume Ramp Up Time (B) For fS = 32 kHz ® 10 ms For fS = 48 kHz ® 8 ms ADC Power UP Wait 20 ms Restore Previous Volume Level (Ramp) in (B) ms Record - Continue F0023-02 Figure 5-16.
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TLV320AIC3100 SLAS667A – NOVEMBER 2009 – REVISED MAY 2012 www.ti.com D-S ADC Signal Processing Blocks DOUT DIG_MIC_IN Mono ADC CIC Filter ADC_MOD_CLK SDIN GPIO1 Figure 5-17. Digital Microphone in the TLV320AIC3100 The TLV320AIC3100 outputs internal clock ADC_MOD_CLK on the GPIO1 pin (page 0 / register 51, bits D5–D2 = 1010). This clock can be connected to the external digital microphone device. The single-bit output of the external digital microphone device can be connected to the DIN pin.
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TLV320AIC3100 www.ti.com SLAS667A – NOVEMBER 2009 – REVISED MAY 2012 Mode B To choose mode B, page 0 / register 102, bit D5 must be programmed to 1. In dc-measurement mode B, a first-order IIR filter is used. The coefficients of this filter are determined by D, page 0 / register 102, bits D4–D0. The nature of the filter is given in Table 5-24. Table 5-24. DC Measurement Bandwidth Settings D: Page 0 / Register 102, Bits D4–D0 –3 dB BW (Hz) –0.
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TLV320AIC3100 SLAS667A – NOVEMBER 2009 – REVISED MAY 2012 www.ti.com images strongly suppressed within the audio band to beyond 20 kHz. To handle multiple input rates and optimize power dissipation and performance, the TLV320AIC3100 allows the system designer to program the oversampling rates over a wide range from 1 to 1024 by configuring page 0 / register 13 and page 0 / register 14.
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TLV320AIC3100 www.ti.com SLAS667A – NOVEMBER 2009 – REVISED MAY 2012 Table 5-25. Overview – DAC Predefined Processing Blocks Processing Block No.
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TLV320AIC3100 SLAS667A – NOVEMBER 2009 – REVISED MAY 2012 www.ti.com 5.5.1.2.3 Six Biquads, First-Order IIR, Filter A or B BiQuad A IIR from Interface BiQuad B BiQuad C BiQuad D BiQuad E Interp. Filter A,B BiQuad F ´ to Modulator Digital Volume Ctrl Figure 5-21. Signal Chain for PRB_P3, PRB_P6, PRB_P11, and PRB_P16 5.5.1.2.4 IIR, Filter B or C Interp. Filter B,C IIR from Interface ´ to Modulator Digital Volume Ctrl Figure 5-22. Signal Chain for PRB_P7, PRB_P12, PRB_P17, and PRB_P20 5.5.1.2.
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TLV320AIC3100 www.ti.com SLAS667A – NOVEMBER 2009 – REVISED MAY 2012 5.5.1.2.8 Four Biquads, First-Order IIR, Filter C IIR from Interface BiQuad A BiQuad B BiQuad C BiQuad D Interp. Filter C ´ to modulator Digital Volume Ctrl Figure 5-26. Signal Chain for PRB_P19 and PRB_P22 5.5.1.2.9 Two Biquads, 3D, Filter A From LeftChannel Interface + Biquad BL + Biquad CL Interp.
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TLV320AIC3100 SLAS667A – NOVEMBER 2009 – REVISED MAY 2012 www.ti.com 5.5.1.2.10 Five Biquads, DRC, 3D, Filter A IIR from Left Left Channel Interface + BiQuad CL BiQuad BL + BiQuad DL BiQuad EL BiQuad FL ´ Interp. Filter A to Modulator + HPF + BiQuad AL + - Digital Volume Ctrl DRC 3D PGA BiQuad AR from Right Channel Interface IIR Right + BiQuad BR + BiQuad CR BiQuad DR BiQuad ER BiQuad FR HPF ´ Interp. Filter A to Modulator Digital Volume Ctrl DRC Figure 5-28.
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TLV320AIC3100 www.ti.com 5.5.1.3 SLAS667A – NOVEMBER 2009 – REVISED MAY 2012 DAC User-Programmable Filters Depending on the selected processing block, different types and orders of digital filtering are available. Up to six biquad sections are available for specific processing blocks. The coefficients of the available filters are arranged as sequentially-indexed coefficients in two banks. If adaptive filtering is chosen, the coefficient banks can be switched in real time.
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TLV320AIC3100 SLAS667A – NOVEMBER 2009 – REVISED MAY 2012 www.ti.com Table 5-27. DAC IIR Filter Coefficients Filter Coefficient First-order IIR N0 Page 9 / register 2 and page 9 / register 3 Left DAC Channel Page 9 / register 8 and page 9 / register 9 Right DAC Channel 0x7FFF (decimal 1.
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TLV320AIC3100 www.ti.com SLAS667A – NOVEMBER 2009 – REVISED MAY 2012 Table 5-28. DAC Biquad Filter Coefficients (continued) Filter Coefficient Biquad D Biquad E Biquad F 5.5.1.4 Left DAC Channel Right DAC Channel Default (Reset) Value N0 Page 8 / register 32 and page 8 / register 33 Page 8 / register 96 and page 8 / register 97 0x7FFF (decimal 1.
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TLV320AIC3100 SLAS667A – NOVEMBER 2009 – REVISED MAY 2012 www.ti.com DAC Channel Response for Interpolation Filter A (Red Line Corresponds to –65 dB) 0 –10 Magnitude – dB –20 –30 –40 –50 –60 –70 –80 –90 1 2 5 6 3 4 Frequency Normalized to fS 7 Figure 5-30. Frequency Response of DAC Interpolation Filter A 5.5.1.4.2 Interpolation Filter B Filter B is specifically designed for an fS up to 96 ksps. Thus, the flat pass-band region easily covers the required audio band of 0 kHz–20 kHz. Table 5-30.
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TLV320AIC3100 www.ti.com SLAS667A – NOVEMBER 2009 – REVISED MAY 2012 DAC Channel Response for Interpolation Filter C (Red Line Corresponds to –43 dB) 0 Magnitude – dB –10 –20 –30 –40 –50 –60 –70 0 0.2 0.4 0.6 0.8 1 1.2 Frequency Normalized to fS 1.4 Figure 5-32. Frequency Response of DAC Interpolation Filter C Table 5-31. Specification for DAC Interpolation Filter C Parameter Condition Value (Typical) Unit Filter-gain pass band 0 … 0.35 fS ±0.03 dB Filter-gain stop band 0.6 fS … 1.
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TLV320AIC3100 SLAS667A – NOVEMBER 2009 – REVISED MAY 2012 5.5.3 www.ti.com Volume-Control Pin The volume-control pin is not enabled by default but it can be enabled by writing 1 to page 0 / register 116, bit D7. The default DAC volume control uses software control of the volume, which occurs if page 0 / register 116, bit D7 = 0. Soft-stepping the volume level is set up by writing to page 0 / register 63, bits D1–D0.
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TLV320AIC3100 www.ti.com SLAS667A – NOVEMBER 2009 – REVISED MAY 2012 The VOL/MICDET pin connection and functionality are shown in Figure 5-33. 24 dB to Mute Digital DAC_L D-S DAC Vol Ctl Processing Blocks 24 dB to Mute AVDD Digital VREF IN R1 AVDD VOL/ MICDET DAC_R D-S DAC Vol Ctl Processing Blocks 18 dB to Mute P1 7- Bit ADC R2 CVOL Tone Generator and Mixer Are NOT Shown 24 dB to Mute Volume Level Register Controlled AVSS B0210-08 Figure 5-33.
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TLV320AIC3100 SLAS667A – NOVEMBER 2009 – REVISED MAY 2012 www.ti.com DRC can be disabled by writing to page 0 / register 68, bits D6–D5. DRC typically works on the filtered version of the input signal. The input signals have no audio information at dc and extremely low frequencies; however, they can significantly influence the energy estimation function in the dynamic range compressor (the DRC).
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TLV320AIC3100 www.ti.com 5.5.4.2 SLAS667A – NOVEMBER 2009 – REVISED MAY 2012 DRC Hysteresis DRC hysteresis is programmable by writing to page 0 / register 68, bits D1–D0. These bits can be programmed to represent values between 0 dB and 3 dB in steps of 1 dB. It is a programmable window around the programmed DRC threshold that must be exceeded for the disabled DRC to become enabled, or the enabled DRC to become disabled.
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TLV320AIC3100 SLAS667A – NOVEMBER 2009 – REVISED MAY 2012 5.5.4.6 • • • • • • www.ti.com Example Setup for DRC PGA gain = 12 dB Threshold = –24 dB Hysteresis = 3 dB Hold time = 0 ms Attack rate = 1.9531e–4 dB per sample period Decay rate = 2.4414e–5 dB per sample period Script #Go to Page 0 w 30 00 00 #DAC => 12 db gain left w 30 41 18 #DAC => 12 db gain right w 30 42 18 #DAC => DRC Enabled for both channels, Threshold = -24 db, Hysteresis = 3 dB w 30 44 7F #DRC Hold = 0 ms, Rate of Changes of Gain = 0.
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TLV320AIC3100 www.ti.com SLAS667A – NOVEMBER 2009 – REVISED MAY 2012 This feature is enabled by programming page 0 / register 67, bit D1. In order to avoid false detections due to mechanical vibrations in headset jacks or microphone buttons, a debounce function is provided for glitch rejection. For the case of headset insertion, a debounce function with a range of 32 ms to 512 ms is provided. This can be programmed via page 0 / register 67, bits D4–D2.
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TLV320AIC3100 SLAS667A – NOVEMBER 2009 – REVISED MAY 2012 www.ti.com Each of these INT1 and INT2 interrupts can be routed to output pins GPIO1 or DOUT. These interrupt signals can either be configured as a single pulse or a series of pulses by programming page 0 / register 48, bit D0 and page 0 / register 49, bit D0.
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TLV320AIC3100 www.ti.com SLAS667A – NOVEMBER 2009 – REVISED MAY 2012 fin = Beep frequency desired fS = Sample rate Cycle = Number of beep (sine wave) cycles that are needed dec2hex = Decimal to hexadecimal conversion function NOTES: 1. fin should be less than fS/4. 2. For the sine and cosine values, if the number of bits is less than the full 16-bit value, then the unused MSBs must be written as 0s. 3.
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TLV320AIC3100 SLAS667A – NOVEMBER 2009 – REVISED MAY 2012 www.ti.com Play - Paused Volume Ramp Down Soft Mute Wait (A) ms DAC Volume Ramp Down WAIT Time (A) For fS = 32 kHz ® Wait 25 ms (min) DAC Power Down Update Digital Filter Coefficients For fS = 48 kHz ® Wait 20 ms (min) DAC Volume Ramp Up Time (B) For fS = 32 kHz ® 25 ms DAC Power UP For fS = 48 kHz ® 20 ms Wait 20 ms Restore Previous Volume Level (Ramp) in (B) ms Play - Continue F0024-02 Figure 5-35.
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TLV320AIC3100 www.ti.com SLAS667A – NOVEMBER 2009 – REVISED MAY 2012 5.5.11 Analog Audio Routing The TLV320AIC3100 has the capability to route the DAC output to either the headphone or the speaker output. If desirable, both output drivers can be operated at the same time while playing at different volume levels. The TLV320AIC3100 provides various digital routing capabilities, allowing digital mixing or even channel swapping in the digital domain.
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TLV320AIC3100 SLAS667A – NOVEMBER 2009 – REVISED MAY 2012 www.ti.com Table 5-38. Analog Volume Control for Headphone and Speaker Outputs (for D7 = 1) (1) Register Value D6–D0 (1) Analog Gain (dB) Register Value D6–D0 Analog Gain (dB) Register Value D6–D0 Analog Gain (dB) Register Value D6–D0 Analog Gain (dB) 0 0.0 30 –15.0 60 –30.1 90 –45.2 1 –0.5 31 –15.5 61 –30.6 91 –45.8 2 –1.0 32 –16.0 62 –31.1 92 –46.2 3 –1.5 33 –16.5 63 –31.6 93 –46.7 4 –2.0 34 –17.
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TLV320AIC3100 www.ti.com SLAS667A – NOVEMBER 2009 – REVISED MAY 2012 5.5.12 Analog Outputs Various analog routings are supported for playback. All the options can be conveniently viewed on the functional block diagram, Figure 1-1. 5.5.12.1 Headphone Drivers The TLV320AIC3100 features a stereo headphone driver (HPL and HPR) that can deliver up to 30 mW per channel, at 3.3-V supply voltage, into a 16-Ω load.
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TLV320AIC3100 SLAS667A – NOVEMBER 2009 – REVISED MAY 2012 www.ti.com The TLV320AIC3100 has a short-circuit protection feature for the speaker drivers that is always enabled to provide protection. If the output is shorted, the output stage shuts down on the overcurrent condition. (Current limiting is not an available option for the higher-current speaker driver output stage.
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TLV320AIC3100 www.ti.com SLAS667A – NOVEMBER 2009 – REVISED MAY 2012 BCLK MCLK DIN GPIO1 PLL_CLKIN PLL ´ (R ´ J.D)/P BCLK MCLK GPIO1 PLL_CLK CODEC_CLKIN ¸ NDAC To DAC_PRB Clock Generation NDAC = 1, 2, ..., 127, 128 ¸ NADC NADC = 1, 2, ..., 127, 128 DAC_CLK To ADC_PRB Clock Generation ADC_CLK ¸ MDAC MDAC = 1, 2, ..., 127, 128 ¸ MADC MADC = 1, 2, ..., 127, 128 ADC_MOD_CLK DAC_MOD_CLK ¸ DOSR DOSR = 1, 2, ..., 1023, 1024 ¸ AOSR DAC_fS AOSR = 1, 2, ...
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TLV320AIC3100 SLAS667A – NOVEMBER 2009 – REVISED MAY 2012 www.ti.com Table 5-40. CODEC CLKIN Clock Dividers (continued) Divider Bits NADC Page 0 / register 18, bits D6–D0 MADC Page 0 / register 19, bits D6–D0 AOSR Page 0 / register 20, bits D7–D0 The DAC modulator is clocked by DAC_MOD_CLK. For proper power-up operation of the DAC channel, DAC_MOD_CLK must be enabled by configuring the NDAC and MDAC clock dividers (page 0 / register 11, bit D7 = 1 and page 0 / register 12, bit D7 = 1).
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TLV320AIC3100 www.ti.com SLAS667A – NOVEMBER 2009 – REVISED MAY 2012 In the mode when the TLV320AIC3100 is configured to drive the BCLK pin (page 0 / register 27, bit D3 = 1), it can be driven as the divided value of BDIV_CLKIN. The division value can be programmed from 1 to 128 in page 0 / register 30, bits D6–D0.
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TLV320AIC3100 SLAS667A – NOVEMBER 2009 – REVISED MAY 2012 5.6.1 www.ti.com PLL For lower power consumption, it is best to derive the internal audio processing clocks using the simple dividers. When the input MCLK or other source clock is not an integer multiple of the audio processing clocks, then it is necessary to use the on-board PLL. The TLV320AIC3100 fractional PLL can be used to generate an internal master clock used to produce the processing clocks needed by the ADC, DAC, and processing blocks.
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TLV320AIC3100 www.ti.com SLAS667A – NOVEMBER 2009 – REVISED MAY 2012 Table 5-42. PLL Example Configurations PLL_CLKIN (MHz) PLLP PLLR PLLJ 2.8224 1 3 10 5.6448 PLLD MADC NADC AOSR MDAC NDAC DOSR 0 3 5 128 3 5 128 fS = 44.1 kHz 1 3 5 0 3 5 128 3 5 128 12 1 1 7 560 3 5 128 3 5 128 13 1 1 6 3504 2 9 104 6 3 104 16 1 1 5 2920 3 5 128 3 5 128 19.2 1 1 4 4100 3 5 128 3 5 128 48 4 1 7 560 3 5 128 3 5 128 2.
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TLV320AIC3100 SLAS667A – NOVEMBER 2009 – REVISED MAY 2012 5.7 www.ti.com Digital Audio and Control Interface 5.7.1 Digital Audio Interface Audio data is transferred between the host processor and the TLV320AIC3100 via the digital audio data serial interface, or audio bus.
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TLV320AIC3100 www.ti.com SLAS667A – NOVEMBER 2009 – REVISED MAY 2012 1/fs WCLK BCLK Left Channel DIN/DOUT 0 n-1 n-2 n-3 Right Channel 2 MSB 1 0 n-1 n-2 n-3 LSB 2 MSB 1 0 LSB Figure 5-40. Timing Diagram for Right-Justified Mode For the right-justified mode, the number of bit clocks per frame should be greater than or equal to twice the programmed word length of the data. 5.7.1.
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TLV320AIC3100 SLAS667A – NOVEMBER 2009 – REVISED MAY 2012 WORD CLOCK www.ti.com LEFT CHANNEL RIGHT CHANNEL BIT CLOCK N N N - - 1 2 3 DATA 3 2 1 N N N - - 1 2 3 0 LD(n) 3 2 1 N N N - - 1 2 3 0 RD(n) LD(n) = n'th sample of left channel data 3 LD(n+1) RD(n) = n'th sample of right channel data Figure 5-43.
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TLV320AIC3100 www.ti.com SLAS667A – NOVEMBER 2009 – REVISED MAY 2012 WORD CLOCK LEFT CHANNEL RIGHT CHANNEL BIT CLOCK DATA N N N - - 1 2 3 3 2 1 N N N - - 1 2 3 0 LD(n) 3 2 1 N N N - - 1 2 3 0 RD(n) LD(n) = n'th sample of left channel data 3 LD(n+1) RD(n) = n'th sample of right channel data Figure 5-46.
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TLV320AIC3100 www.ti.com 0 LSB 1 2 MSB n–1 n–2 n–3 0 LSB 1 2 MSB n–1 n–2 n–3 0 LSB 0 LSB n–1 n–2 n–3 1 2 n–1 n–2 n–3 MSB DOUT BCLK WCLK 1 Clock Before MSB 1/fS MSB 2 1 ADC Mono Channel (D0) ADC Mono Channel (D0) ADC Mono Channel (D1) 1/fS ADC Mono Channel (D1) n–1 T0202-03 SLAS667A – NOVEMBER 2009 – REVISED MAY 2012 Figure 5-47.
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TLV320AIC3100 www.ti.com 5.7.1.4 SLAS667A – NOVEMBER 2009 – REVISED MAY 2012 DSP Mode The audio interface of the TLV320AIC3100 can be put into DSP mode by programming page 0 / register 27, bits D7–D6 = 01. In DSP mode, the falling edge of the word clock starts the data transfer with the left-channel data first and immediately followed by the right-channel data. Each data bit is valid on the falling edge of the bit clock.
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TLV320AIC3100 SLAS667A – NOVEMBER 2009 – REVISED MAY 2012 5.7.2 www.ti.com Primary and Secondary Digital Audio Interface Selection The audio serial interface on the TLV320AIC3100 has extensive I/O control to allow communication with two independent processors for audio data. The processors can communicate with the device one at a time. This feature is enabled by register programming of the various pin selections. Table 5-43 shows the primary and secondary audio interface selection and registers.
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TLV320AIC3100 www.ti.com SLAS667A – NOVEMBER 2009 – REVISED MAY 2012 Table 5-44.
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TLV320AIC3100 SLAS667A – NOVEMBER 2009 – REVISED MAY 2012 5.7.3.1 www.ti.com I2C Control Mode The TLV320AIC3100 supports the I2C control protocol, and responds to the I2C address of 0011 000. I2C is a two-wire, open-drain interface supporting multiple devices and masters on a single bus. Devices on the I2C bus only drive the bus lines LOW by connecting them to ground; they never drive the bus lines HIGH.
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TLV320AIC3100 www.ti.com SLAS667A – NOVEMBER 2009 – REVISED MAY 2012 SCL DA(6) SDA Start (M) DA(0) 7-bit Device Address (M) RA(7) Write (M) Slave Ack (S) RA(0) 8-bit Register Address (M) D(7) Slave Ack (S) D(0) 8-bit Register Data (M) Slave Ack (S) Stop (M) (M) => SDA Controlled by Master (S) => SDA Controlled by Slave Figure 5-52.
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TLV320AIC3100 SLAS667A – NOVEMBER 2009 – REVISED MAY 2012 www.ti.com 6 REGISTER MAP 6.1 TLV320AIC3100 Register Map All features on this device are addressed using the I2C bus. All of the writable registers can be read back. However, some registers contain status information or data, and are available for reading only. The TLV320AIC3100 contains several pages of 8-bit registers, and each page can contain up to 128 registers. The register pages are divided up based on functional blocks for this device.
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TLV320AIC3100 www.ti.com SLAS667A – NOVEMBER 2009 – REVISED MAY 2012 Page 0 / Register 3: OT FLAG D7-D2 D1 READ/ WRITE R R RESET VALUE XXXX 1 D0 R/W XX BIT DESCRIPTION Reserved. Do not write to these bits. 0: Overtemperature protection flag (active-low). Valid only if speaker amplifier is powered up 1: Normal operation Reserved. Do not write to these bits.
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TLV320AIC3100 SLAS667A – NOVEMBER 2009 – REVISED MAY 2012 www.ti.com Page 0 / Register 8: PLL D-VAL LSB (1) BIT D7–D0 (1) READ/ WRITE R/W RESET VALUE 0000 0000 DESCRIPTION PLL fractional multiplier D-Val LSB bits D[7:0] Note that page 0 / Register 8 must be written immediately after page 0 / Register 7.
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TLV320AIC3100 www.ti.com SLAS667A – NOVEMBER 2009 – REVISED MAY 2012 Page 0 / Register 15: DAC IDAC_VAL (1) BIT D7–D0 (1) READ/ WRITE R/W RESET VALUE 1000 0000 DESCRIPTION 0000 0000: 0000 0001: 0000 0010: ...
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TLV320AIC3100 SLAS667A – NOVEMBER 2009 – REVISED MAY 2012 www.ti.com Page 0 / Registers 21: ADC IADC_VAL (1) BIT D7–D0 (1) READ/ WRITE R/W RESET VALUE 1000 0000 DESCRIPTION 0000 0000: Reserved 0000 0001: Number of instruction 0000 0010: Number of instruction ...
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TLV320AIC3100 SLAS667A – NOVEMBER 2009 – REVISED MAY 2012 www.ti.com Page 0 / Register 31: Codec Secondary Interface Control 1 D7–D5 READ/ WRITE R/W RESET VALUE 000 D4–D2 R/W 000 D1–D0 R/W 00 D7–D5 READ/ WRITE R/W RESET VALUE 000 D4 D3 R/W R/W 0 0 D2 R/W 0 D1 R/W 0 D0 R/W 0 D7 READ/ WRITE R/W RESET VALUE 0 D6 R/W 0 D5–D4 R/W 00 D3–D2 R/W 00 D1 R/W 0 D0 R/W 0 BIT DESCRIPTION 000: Secondary BCLK is obtained from GPIO1 pin.
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TLV320AIC3100 www.ti.com SLAS667A – NOVEMBER 2009 – REVISED MAY 2012 Page 0 / Register 34: I2C Bus Condition D7–D6 D5 READ/ WRITE R/W R/W RESET VALUE 00 0 D4–D0 R/W 0 0000 READ/ WRITE R/W RESET VALUE XXXX XXXX D7 READ/ WRITE R RESET VALUE 0 D6 R 0 D5 (1) R 0 D4–D0 R/W X XXXX BIT DESCRIPTION Reserved. Write only the reset value to these bits. 0: I2C general-call address is ignored. 1: Device accepts I2C general-call address. Reserved. Write only zeros to these bits.
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TLV320AIC3100 SLAS667A – NOVEMBER 2009 – REVISED MAY 2012 www.ti.com Page 0 / Register 39: Overflow Flags D7 (1) READ/ WRITE R RESET VALUE 0 D6 (1) R 0 D5 (1) R 0 D4 D3 (1) R/W R 0 0 D2 D1 (1) R/W R 0 0 D0 R/W 0 BIT (1) DESCRIPTION Left-Channel DAC Overflow Flag 0: Overflow has not occurred. 1: Overflow has occurred. Right-Channel DAC Overflow Flag 0: Overflow has not occurred. 1: Overflow has occurred. DAC Barrel Shifter Output Overflow Flag 0: Overflow has not occurred.
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TLV320AIC3100 www.ti.com SLAS667A – NOVEMBER 2009 – REVISED MAY 2012 Page 0 / Register 45: Interrupt Flags—ADC D7 D6 (1) READ/ WRITE R/W R RESET VALUE 0 0 D5 D4 (1) R/W R 0 X D3 (1) R X D2 R 0 D1–D0 R/W 00 BIT (1) DESCRIPTION Reserved. Write only zero to this bit. 0: ADC signal power greater than noise threshold for AGC. 1: ADC signal power less than noise threshold for AGC. Reserved. Write only zeros to these bits.
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TLV320AIC3100 SLAS667A – NOVEMBER 2009 – REVISED MAY 2012 www.ti.com Page 0 / Register 48: INT1 Control Register D7 READ/ WRITE R/W RESET VALUE 0 D6 R/W 0 D5 R/W 0 D4 R/W 0 D3 R/W 0 D2 R/W 0 D1 R/W 0 D0 R/W 0 BIT DESCRIPTION 0: Headset-insertion detect interrupt is not used in the generation of INT1 interrupt. 1: Headset-insertion detect interrupt is used in the generation of INT1 interrupt. 0: Button-press detect interrupt is not used in the generation of INT1 interrupt.
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TLV320AIC3100 www.ti.com SLAS667A – NOVEMBER 2009 – REVISED MAY 2012 Page 0 / Register 51: GPIO1 In/Out Pin Control D7–D6 D5–D2 READ/ WRITE R/W R/W RESET VALUE XX 0000 D1 D0 R R/W X 0 READ/ WRITE R/W RESET VALUE XXXX XXXX D7–D5 D4 READ/ WRITE R/W R/W RESET VALUE 000 1 D3–D1 R/W 001 D0 R/W 0 BIT DESCRIPTION Reserved. Do not write any value other than reset value.
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TLV320AIC3100 SLAS667A – NOVEMBER 2009 – REVISED MAY 2012 www.ti.com Page 0 / Register 56: Reserved BIT D7–D0 READ/ WRITE R/W RESET VALUE 0000 001X READ/ WRITE R/W RESET VALUE 000X 000X READ/ WRITE R/W RESET VALUE 000X 0000 READ/ WRITE R/W RESET VALUE 0000 0000 READ/ WRITE R/W R/W RESET VALUE 000 0 0001 READ/ WRITE R/W R/W RESET VALUE 000 0 0100 DESCRIPTION Reserved Page 0 / Register 57: Reserved BIT D7–D0 DESCRIPTION Reserved. Write only reset value.
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TLV320AIC3100 SLAS667A – NOVEMBER 2009 – REVISED MAY 2012 www.ti.com Page 0 / Register 65: DAC Left Volume Control BIT D7–D0 READ/ WRITE R/W RESET VALUE 0000 0000 DESCRIPTION 0111 1111–0111 0001: Reserved. Do not write these sequences to these bits. 0011 0000 : Left-channel DAC digital gain = 24 dB 0010 1111: Left-channel DAC digital gain = 23.5 dB 0010 1110: Left-channel DAC digital gain = 23 dB ... 0000 0001: Left-channel DAC digital gain = 0.
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TLV320AIC3100 www.ti.com SLAS667A – NOVEMBER 2009 – REVISED MAY 2012 Page 0 / Register 68: DRC Control 1 D7 D6 READ/ WRITE R/W R/W RESET VALUE 0 0 D5 R/W 0 D4–D2 R/W 011 D1–D0 R/W 11 READ/ WRITE R R/W RESET VALUE 0 0111 BIT DESCRIPTION Reserved. Write only the reset value to these bits.
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TLV320AIC3100 SLAS667A – NOVEMBER 2009 – REVISED MAY 2012 www.ti.com Page 0 / Register 71: Left Beep Generator D7 READ/ WRITE R/W RESET VALUE 0 D6 D5–D0 R/W R/W 0 00 0000 BIT (1) (1) DESCRIPTION 0: Beep generator is disabled. 1: Beep generator is enabled (self-clearing based on beep duration). Reserved. Write only reset value.
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TLV320AIC3100 www.ti.com SLAS667A – NOVEMBER 2009 – REVISED MAY 2012 Page 0 / Register 79: Beep Cos(x) LSB READ/ WRITE R/W RESET VALUE 1110 0011 READ/ WRITE R/W RESET VALUE XXXX XXXX D7 READ/ WRITE R/W RESET VALUE 0 D6 D5–D4 R/W R/W 0 00 D3 R/W 0 D2 D1–D0 R/W R/W 0 00 D7 READ/ WRITE R/W RESET VALUE 1 D6–D4 R/W 000 D3–D0 R/W 0000 BIT D7–D0 DESCRIPTION 8 LSBs out of 16 bits for cos(2π × fin/fS), where fin is the beep frequency and fS is the DAC sample rate.
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TLV320AIC3100 SLAS667A – NOVEMBER 2009 – REVISED MAY 2012 www.ti.com Page 0 / Registers 84–85: Reserved READ/ WRITE R/W RESET VALUE XXXX XXXX D7 READ/ WRITE R/W RESET VALUE 0 D6–D4 R/W 000 D3–D0 R/W 0000 D7–D6 READ/ WRITE R/W RESET VALUE 00 D5–D1 R/W 00 000 D0 R/W 0 BIT D7 DESCRIPTION Reserved. Write only the reset value to these bits. Page 0 / Register 86: AGC Control 1 BIT DESCRIPTION 0: AGC disabled 1: AGC enabled 000: AGC target level = –5.
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TLV320AIC3100 SLAS667A – NOVEMBER 2009 – REVISED MAY 2012 www.ti.com Page 0 / Register 92: AGC Signal Debounce BIT D7–D4 D3–D0 READ/ WRITE R/W R/W RESET VALUE 0000 0000 DESCRIPTION Reserved. Write only zeros to these bits.
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TLV320AIC3100 www.ti.com SLAS667A – NOVEMBER 2009 – REVISED MAY 2012 Page 0 / Register 103: ADC DC Measurement 2 D7 D6 READ/ WRITE R/W R/W RESET VALUE 0 0 D5 R/W 0 D4–D0 R/W 0 0000 BIT DESCRIPTION Reserved. Write only reset value. 0: DC measurement data update is enabled. 1: DC measurment data update is disabled. User can read the last updated data without any data corruption. 0: For IIR-based dc measurement, the measurment value is the instantaneous output of the IIR filter.
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TLV320AIC3100 SLAS667A – NOVEMBER 2009 – REVISED MAY 2012 www.ti.com Page 0 / Register 116: VOL/MICDET-Pin SAR ADC – Volume Control D7 READ/ WRITE R/W RESET VALUE 0 D6 R/W 0 D5–D4 R/W 00 D3 D2–D0 R/W R/W 0 000 BIT DESCRIPTION 0: DAC volume control is controlled by control register (7-bit Vol ADC is powered down). 1: DAC volume control is controlled by pin. 0: Internal on-chip RC oscillator is used for the 7-bit Vol ADC for pin volume control.
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TLV320AIC3100 www.ti.com SLAS667A – NOVEMBER 2009 – REVISED MAY 2012 Page 1 / Registers 1–29: Reserved READ/ WRITE R/W RESET VALUE XXXX XXXX D7–D2 D1 READ/ WRITE R/W R/W RESET VALUE 0000 00 0 D0 R/W 0 D7 READ/ WRITE R/W RESET VALUE 0 D6 R/W 0 D5 D4–D3 R/W R/W 0 0 D2 D1 R/W R/W 1 0 D0 R 0 D7 READ/ WRITE R/W RESET VALUE 0 D6 R/W 0 D5–D1 D0 R/W R 00 011 0 BIT D7–D0 DESCRIPTION Reserved. Do not write to these registers.
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TLV320AIC3100 SLAS667A – NOVEMBER 2009 – REVISED MAY 2012 www.ti.com Page 1 / Register 33 (0x21): HP Output Drivers POP Removal Settings D7 READ/ WRITE R/W RESET VALUE 0 D6–D3 R/W 0111 D2–D1 R/W 11 D0 R/W 0 D7 D6–D4 READ/ WRITE R/W R/W RESET VALUE 0 000 D3–D0 R/W 0000 BIT DESCRIPTION 0: If power-down sequence is activated by device software power down using page 1 / register 46, bit D7, then power down the DAC simultaneously with the HP and SP amplifiers.
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TLV320AIC3100 www.ti.com SLAS667A – NOVEMBER 2009 – REVISED MAY 2012 Page 1 / Register 35: DAC_L and DAC_R Output Mixer Routing� � D7–D6 READ/ WRITE R/W RESET VALUE 00 D5 R/W 0 BIT D4 0 D3–D2 R/W 00 D1 R/W 0 D0 R/W 0 D7 READ/ WRITE R/W RESET VALUE 0 D6–D0 R/W 111 1111 D7 READ/ WRITE R/W RESET VALUE 0 D6–D0 R/W 111 1111 DESCRIPTION 00: DAC_L is not routed anywhere. 01: DAC_L is routed to the left-channel mixer amplifier. 10: DAC_L is routed directly to the HPL driver.
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TLV320AIC3100 SLAS667A – NOVEMBER 2009 – REVISED MAY 2012 www.ti.com Page 1 / Register 40 (0x28): HPL Driver D7 D6–D3 READ/ WRITE R/W R/W RESET VALUE 0 0000 D2 R/W 0 D1 R/W 1 D0 R 0 BIT (1) DESCRIPTION Reserved. Write only zero to this bit. 0000: HPL driver PGA = 0 dB 0001: HPL driver PGA = 1 dB 0010: HPL driver PGA = 2 dB ... 1000: HPL driver PGA = 8 dB 1001: HPL driver PGA = 9 dB 1010–1111: Reserved. Do not write these sequences to these bits. 0: HPL driver is muted.
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TLV320AIC3100 www.ti.com SLAS667A – NOVEMBER 2009 – REVISED MAY 2012 Page 1 / Register 43: Reserved D7–D5 D4–D3 READ/ WRITE R/W R/W RESET VALUE 000 00 D2 R/W 0 D1 D0 R/W R 0 0 D7–D5 READ/ WRITE R/W RESET VALUE 000 D4–D3 R/W 00 D2 R/W 0 D1 R/W 0 D0 R/W 0 BIT DESCRIPTION Reserved. Write only zeros to these bits. 00: Reserved 01: Reserved 10: Reserved 11: Reserved 0: Reserved 1: Reserved Reserved. Write only zero to this bit.
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TLV320AIC3100 SLAS667A – NOVEMBER 2009 – REVISED MAY 2012 www.ti.com Page 1 / Register 47: MIC PGA D7 READ/ WRITE R/W RESET VALUE 1 D6–D0 R/W 000 0000 BIT DESCRIPTION 0: MIC PGA is controlled by bits D6–D0. 1: MIC PGA is at 0 dB. 000 0000: PGA = 0 dB 000 0001: PGA = 0.5 dB 000 0010: PGA = 1 dB ... 111 0110: PGA = 59 dB 111 0111: PGA = 59.5 dB 111 1000–111 1111: Reserved. Do not write these sequences to these bits.
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TLV320AIC3100 www.ti.com SLAS667A – NOVEMBER 2009 – REVISED MAY 2012 Page 1 / Registers 51–127: Reserved BIT D7–D0 6.4 READ/ WRITE R/W RESET VALUE XXXX XXXX DESCRIPTION Reserved. Write only the reset value to these bits. Control Registers, Page 3: MCLK Divider for Programmable Delay Timer Default values shown for this page only become valid 100 μs following a hardware or software reset. Table 6-3.
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TLV320AIC3100 SLAS667A – NOVEMBER 2009 – REVISED MAY 2012 www.ti.com Table 6-5.
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TLV320AIC3100 www.ti.com SLAS667A – NOVEMBER 2009 – REVISED MAY 2012 Table 6-5.
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TLV320AIC3100 SLAS667A – NOVEMBER 2009 – REVISED MAY 2012 www.ti.com The remaining page-8 registers are either reserved registers or are used for setting coefficients for the various filters in the TLV320AIC3100. Reserved registers should not be written to. The filter coefficient registers are arranged in pairs, with two adjacent 8-bit registers containing the 16-bit coefficient for a single filter.
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TLV320AIC3100 www.ti.com SLAS667A – NOVEMBER 2009 – REVISED MAY 2012 Table 6-6.
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TLV320AIC3100 SLAS667A – NOVEMBER 2009 – REVISED MAY 2012 www.ti.com Table 6-6.
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TLV320AIC3100 www.ti.com 6.7 SLAS667A – NOVEMBER 2009 – REVISED MAY 2012 Control Registers, Page 9: DAC Digital Filter Coefficients Default values shown for this page only become valid 100 μs following a hardware or software reset. Page 9 / Register 0: Page Control Register READ/ WRITE R/W BIT D7–D0 RESET VALUE 0000 0000 DESCRIPTION 0000 0000: 0000 0001: ...
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TLV320AIC3100 SLAS667A – NOVEMBER 2009 – REVISED MAY 2012 6.8 www.ti.com Control Registers, Page 12: DAC Programmable Coefficients Buffer B (1:63) Table 6-8. Page-12 DAC Buffer B Registers 118 REGISTER NUMBER RESET VALUE 1 0000 0000 Reserved. Do not write to this register.
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TLV320AIC3100 www.ti.com SLAS667A – NOVEMBER 2009 – REVISED MAY 2012 Table 6-8.
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TLV320AIC3100 SLAS667A – NOVEMBER 2009 – REVISED MAY 2012 www.ti.com Table 6-8.
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TLV320AIC3100 www.ti.com 6.9 SLAS667A – NOVEMBER 2009 – REVISED MAY 2012 Control Registers, Page 13: DAC Programmable Coefficients RAM Buffer B (65:127) Table 6-9. Page-13 DAC Buffer B Registers REGISTER NUMBER RESET VALUE 1 0000 0000 Reserved. Do not write to this register.
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TLV320AIC3100 SLAS667A – NOVEMBER 2009 – REVISED MAY 2012 www.ti.com Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision Original (November 2009) to Revision A • • • • • • • • • • • • • • • • 122 Page Added PGA Gain table to Section 5.4.1 ...................................................................................... 27 Deleted Analog Volume Control ... (for D7 = 0) table; modified Analog Volume Control ...
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE MATERIALS INFORMATION www.ti.com 27-Jul-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TLV320AIC3100IRHBR VQFN RHB 32 3000 330.0 12.4 5.3 5.3 1.5 8.0 12.0 Q2 TLV320AIC3100IRHBR VQFN RHB 32 3000 330.0 12.4 5.3 5.3 1.5 8.0 12.0 Q2 TLV320AIC3100IRHBT VQFN RHB 32 250 180.0 12.4 5.3 5.3 1.5 8.0 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 27-Jul-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TLV320AIC3100IRHBR VQFN RHB 32 3000 367.0 367.0 35.0 TLV320AIC3100IRHBR VQFN RHB 32 3000 367.0 367.0 35.0 TLV320AIC3100IRHBT VQFN RHB 32 250 210.0 185.0 35.0 TLV320AIC3100IRHBT VQFN RHB 32 250 210.0 185.0 35.
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