Datasheet

STEREO AUDIO ADC HIGH PASS FILTER
H(z) +
N0 ) N1 z
*1
32768 * D1 z
*1
(1)
DIGITAL AUDIO PROCESSING FOR RECORD PATH
AudioSerialBusInterface
PGA
0/+59.5dB
0.5dBsteps
ADC
+
DAC
L
Volume
Control
DIN
DOUT
BCLK
WCLK
DINL
DINR DOUTL DOUTR
ADC
PGA
0/+59.5dB
0.5dBsteps
+
DACR
Volume
Control
Effects
AGC
AGC
RecordPath
RecordPath
DAC
Powered
Down
DAC
Powered
Down
Effects
SW-D1
SW-D2
SW-D3
SW-D4
LeftChannel
AnalogInputs
RightChannel
AnalogInputs
TLV320AIC3007
SLOS619 – APRIL 2009 ..................................................................................................................................................................................................... www.ti.com
Often in audio applications it is desirable to remove the DC offset from the converted audio data stream. The
TLV320AIC3007 has a programmable first order high pass filter which can be used for this purpose. The Digital
filter coefficients are in 16-bit format and therefore use two 8-bit registers for each of the three coefficients of N0,
N1, and D1. The transfer function of the digital high pass filter is of the form:
Programming the Left channel is done by writing to Page 1, Registers 65-70, and the right channel is
programmed by writing to Page 1, Registers 71-76. After the coefficients have been loaded, these ADC high
pass filter coefficients can be selected by writing to Page 0, Register 107, D7-D6, and the high pass filter can be
enabled by writing to Page 0, Register 12, bits D7-D4.
In applications where record only is selected, and DAC is powered down, the playback path signal processing
blocks can be used in the ADC record path. These filtering blocks can support high pass, low pass, band pass or
notch filtering. In this mode, the record only path has switches SW-D1 through SW-D4 closed, and reroutes the
ADC output data through the digital signal processing blocks. Since the DAC ' s Digital Signal Processing blocks
are being re-used, naturally the addresses of these digital filter coefficients are the same as for the DAC digital
processing and are located on Page 1, Registers 1-52. This record only mode is enabled by powering down both
DACs by writing to Page 0, Register 37, bits D7-D6 (D7=D6= ” 0 ” ). Next, enable the digital filter pathway for the
ADC by writing a “ 1 ” to Page 0, Register 107, bit D3. (Note, this pathway is only enabled if both DACs are
powered down.) This record only path can be seen in Figure 24 .
Figure 24. Record Only Mode With Digital Processing Path Enabled
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