Datasheet

RIGHT JUSTIFIED MODE
BCLK
WCLK
SDIN/
SDOUT
1 00 1 0
1/fs
LSBMSB
LeftChannel RightChannel
2 2
n−1
n−3
n−2
n−1
n−3
n−2
LEFT JUSTIFIED MODE
n-1 n-2 n-3 n-1 n-2 n-3
I
2
S MODE
TLV320AIC3007
www.ti.com ..................................................................................................................................................................................................... SLOS619 – APRIL 2009
When the audio serial data bus is powered down while configured in master mode, the pins associated with the
interface will be put into a 3-state output condition.
In right-justified mode, the LSB of the left channel is valid on the rising edge of the bit clock preceding the falling
edge of word clock. Similarly, the LSB of the right channel is valid on the rising edge of the bit clock preceding
the rising edge of the word clock.
Figure 18. Right Justified Serial Bus Mode Operation
In left-justified mode, the MSB of the right channel is valid on the rising edge of the bit clock following the falling
edge of the word clock. Similarly the MSB of the left channel is valid on the rising edge of the bit clock following
the rising edge of the word clock.
Figure 19. Left Justified Serial Data Bus Mode Operation
In I
2
S mode, the MSB of the left channel is valid on the second rising edge of the bit clock after the falling edge
of the word clock. Similarly the MSB of the right channel is valid on the second rising edge of the bit clock after
the rising edge of the word clock.
Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback 21
Product Folder Link(s) :TLV320AIC3007