Datasheet
OVERVIEW
HARDWARE RESET
I
2
C CONTROL MODE
SDA
SCL
t
HD-STA
0.9 s³ m
t
SU-STO
0.9 s³ m
P
S
t
SU-STA
0.9 s³ m
Sr
t
HD-STA
0.9 s³ m
S
TLV320AIC3007
SLOS619 – APRIL 2009 .....................................................................................................................................................................................................
www.ti.com
The TLV320AIC3007 is a highly flexible, low power, stereo audio codec with extensive feature integration,
intended for applications in smartphones, PDAs, and portable computing, communication, and entertainment
applications. Available in a 5x5mm 40-lead QFN, the product integrates a host of features to reduce cost, board
space, and power consumption in space-constrained, battery-powered, portable applications.
The TLV320AIC3007 consists of the following blocks:
• Stereo audio multi-bit delta-sigma DAC (8 kHz – 96 kHz)
• Stereo audio multi-bit delta-sigma ADC (8 kHz – 96 kHz)
• Programmable digital audio effects processing (3-D, bass, treble, mid-range, EQ, notch filter, de-emphasis)
• Seven audio inputs
• Three high-power audio output drivers (headphone drive capability)
• Two single-ended line output drivers
• Fully programmable PLL
• Headphone/headset jack detection with interrupt
• Differential Class-D speaker driver
Communication to the TLV320AIC3007 for control is via I
2
C. The I
2
C interface supports both standard and fast
communication modes.
The TLV320AIC3007 requires a hardware reset after power-up for proper operation. After all power supplies are
at their specified values, the RESET pin must be driven low for at least 10 ns. If this reset sequence is not
performed, the ' AIC3107 may not respond properly to register reads/writes.
The TLV320AIC3007 supports the I
2
C control protocol using 7-bit addressing, and is capable of both standard
and fast modes. The TLV320AIC3007 responds to the I
2
C address of 001 1000. For I
2
C fast mode, note that the
minimum timing for each of t
HD-STA
, t
SU-STA
, and t
SU-STO
is 0.9 µ s, as seen in Figure 15 .
Figure 15. I2C Fast-Mode Timing Requirements
I
2
C is a two-wire, open-drain interface supporting multiple devices and masters on a single bus. Devices on the
I
2
C bus only drive the bus lines LOW by connecting them to ground; they never drive the bus lines HIGH.
Instead, the bus wires are pulled HIGH by pull-up resistors, so the bus wires are HIGH when no device is driving
them LOW. This way, two devices cannot conflict; if two devices drive the bus simultaneously, there is no driver
contention.
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