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TLV320AIC3007 SLOS619 – APRIL 2009 ..................................................................................................................................................................................................... www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
TLV320AIC3007 www.ti.com ..................................................................................................................................................................................................... SLOS619 – APRIL 2009 AVSS_DAC AVDD_DAC DRVDD DRVSS WCLK BCLK DVDD IOVDD DVSS DOUT DIN AVDD_ADC AVSS_ADC TLV320AIC3007 SIMPLIFIED BLOCK DIAGRAM Audio Serial Bus Interface HPLOUT HPCOM PGA 0/ +59.5dB 0.
TLV320AIC3007 SLOS619 – APRIL 2009 ..................................................................................................................................................................................................... www.ti.
TLV320AIC3007 www.ti.com ..................................................................................................................................................................................................... SLOS619 – APRIL 2009 PIN FUNCTIONS (continued) PIN NAME I/O 26 SPOP O DESCRIPTION 27 NC No Connect 28 NC No Connect 29 NC No Connect 30 NC No Connect 31 RESET I 32 GPIO1 I/O 33 DVDD P Digital core voltage supply, 1.525 V–1.
TLV320AIC3007 SLOS619 – APRIL 2009 ..................................................................................................................................................................................................... www.ti.com RECOMMENDED OPERATING CONDITIONS over operating free-air temperature range (unless otherwise noted) AVDD_DAC, DRVDD (1) Analog supply voltage DVDD (1) IOVDD Digital core supply voltage (1) MIN NOM MAX 2.7 3.3 3.6 V 1.525 1.8 1.
TLV320AIC3007 www.ti.com ..................................................................................................................................................................................................... SLOS619 – APRIL 2009 ELECTRICAL CHARACTERISTICS (continued) At 25°C, AVDD_DAC = 3.3 V, DRVDD = 3.3 V, SPVDD = 5 V, IOVDD = 3.3 V, DVDD = 1.
TLV320AIC3007 SLOS619 – APRIL 2009 ..................................................................................................................................................................................................... www.ti.com ELECTRICAL CHARACTERISTICS (continued) At 25°C, AVDD_DAC = 3.3 V, DRVDD = 3.3 V, SPVDD = 5 V, IOVDD = 3.3 V, DVDD = 1.
TLV320AIC3007 www.ti.com ..................................................................................................................................................................................................... SLOS619 – APRIL 2009 ELECTRICAL CHARACTERISTICS (continued) At 25°C, AVDD_DAC = 3.3 V, DRVDD = 3.3 V, SPVDD = 5 V, IOVDD = 3.3 V, DVDD = 1.8 V, Fs = 48-kHz, 16-bit audio data (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT POWER CONSUMPTION, DRVDD, AVDD_DAC = 3.
TLV320AIC3007 SLOS619 – APRIL 2009 ..................................................................................................................................................................................................... www.ti.com AUDIO DATA SERIAL INTERFACE TIMING DIAGRAMS All specifications at 25°C, DVDD = 1.8 V WCLK td(WS) BCLK td(DO-WS) td(DO-BCLK) SDOUT tS(DI) th(DI) SDIN T0145-01 PARAMETER IOVDD = 1.1 V MIN MAX IOVDD = 3.
TLV320AIC3007 www.ti.com ..................................................................................................................................................................................................... SLOS619 – APRIL 2009 All specifications at 25°C, DVDD = 1.8 V WCLK td(WS) td(WS) BCLK td(DO-BCLK) SDOUT tS(DI) th(DI) SDIN T0146-01 PARAMETER IOVDD = 1.1 V MIN MAX IOVDD = 3.
TLV320AIC3007 SLOS619 – APRIL 2009 ..................................................................................................................................................................................................... www.ti.com All specifications at 25°C, DVDD = 1.8 V WCLK tS(WS) th(WS) tH(BCLK) BCLK td(DO-WS) tL(BCLK) td(DO-BCLK) SDOUT tS(DI) th(DI) SDIN T0145-02 PARAMETER IOVDD = 1.1 V MIN IOVDD = 3.
TLV320AIC3007 www.ti.com ..................................................................................................................................................................................................... SLOS619 – APRIL 2009 All specifications at 25°C, DVDD = 1.8 V WCLK tS(WS) tS(WS) th(WS) th(WS) tL(BCLK) BCLK td(DO-BCLK) tH(BCLK) SDOUT tS(DI) th(DI) SDIN T0146-02 PARAMETER IOVDD = 1.1 V MIN IOVDD = 3.
TLV320AIC3007 SLOS619 – APRIL 2009 ..................................................................................................................................................................................................... www.ti.com TYPICAL CHARACTERISTICS TOTAL HARMONIC DISTORTION vs HEADPHONE OUT POWER SIGNAL-TO-NOISE RATIO vs ADC PGA SETTING 45 0 2.7 VDD_CM 1.35_LDAC 40 3.6 VDD_CM 1.8_LDAC -20 SNR - Signal-To-Noise - dB THD - Total Harmonic Distortion - dB -10 3.3 VDD_CM1.65_LDAC 2.
TLV320AIC3007 www.ti.com ..................................................................................................................................................................................................... SLOS619 – APRIL 2009 TYPICAL CHARACTERISTICS (continued) LEFT DAC FFT 0 Load = 10 kW, FS = 48 kHz, fs = 64 kHz, 4096 Samples, AVDD = DRVDD = 3.
TLV320AIC3007 SLOS619 – APRIL 2009 ..................................................................................................................................................................................................... www.ti.com TYPICAL CHARACTERISTICS (continued) RIGHT ADC FFT 0 Load = 10 kW, FS = 48 kHz, fs = 64 kHz, 2048 Samples, AVDD = DRVDD = 3.3 V, Amplitude - dB -20 -40 -60 -80 -100 -120 -140 -160 0 1 2 3 4 5 6 7 8 9 10 11 12 13 f - Frequency - kHz Figure 12.
TLV320AIC3007 www.ti.com ..................................................................................................................................................................................................... SLOS619 – APRIL 2009 TYPICAL CHARACTERISTICS (continued) TYPICAL CIRCUIT CONFIGURATION IOVDD Multimedia Rp Processor Rp AVDD (2.7V-3.6V) GPIO1 DOUT DIN BCLK WCLK MCLK SDA /RESET SCL AVDD_ADC AVDD_DAC DRVDD DRVDD MICBIAS 1k W 0.1 mF IOVDD (1.1-3.
TLV320AIC3007 SLOS619 – APRIL 2009 ..................................................................................................................................................................................................... www.ti.com OVERVIEW The TLV320AIC3007 is a highly flexible, low power, stereo audio codec with extensive feature integration, intended for applications in smartphones, PDAs, and portable computing, communication, and entertainment applications.
TLV320AIC3007 www.ti.com ..................................................................................................................................................................................................... SLOS619 – APRIL 2009 Communication on the I2C bus always takes place between two devices, one acting as the master and the other acting as the slave. Both masters and slaves can read and write, but slaves can only do so under the direction of the master.
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TLV320AIC3007 www.ti.com ..................................................................................................................................................................................................... SLOS619 – APRIL 2009 When the audio serial data bus is powered down while configured in master mode, the pins associated with the interface will be put into a 3-state output condition.
TLV320AIC3007 SLOS619 – APRIL 2009 ..................................................................................................................................................................................................... www.ti.com n-1 n-2 n-3 n-1 n-2 n-3 Figure 20. I2S Serial Data Bus Mode Operation DSP MODE In DSP mode, the rising edge of the word clock starts the data transfer with the left channel data first and immediately followed by the right channel data.
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TLV320AIC3007 SLOS619 – APRIL 2009 ..................................................................................................................................................................................................... www.ti.com AUDIO DATA CONVERTERS The TLV320AIC3007 supports the following standard audio sampling rates: 8 kHz, 11.025 kHz, 12 kHz, 16 kHz, 22.05 kHz, 24 kHz, 32 kHz, 44.1 kHz, 48 kHz, 88.2 kHz, and 96 kHz.
TLV320AIC3007 www.ti.com ..................................................................................................................................................................................................... SLOS619 – APRIL 2009 MCLK BCLK PLL_CLKIN CLKDIV_CLKIN CLKDIV_IN Q=2,3,…..,16,17 PLL_IN K = J.D J = 1,2,3,…..,62,63 D= 0000,0001,….,9998,9999 R= 1,2,3,4,….,15,16 P= 1,2,….
TLV320AIC3007 SLOS619 – APRIL 2009 ..................................................................................................................................................................................................... www.ti.com When the PLL is enabled, Fsref = (PLLCLK_IN × K × R) / (2048 × P), where P = 1, 2, 3,…, 8 R = 1, 2, …, 16 K = J.
TLV320AIC3007 www.ti.com ..................................................................................................................................................................................................... SLOS619 – APRIL 2009 6.144 1 1 16 0 48000.00 0.0000 8.192 1 1 12.0 1 1 12 0 48000.00 0.0000 8 1920 48000.00 13.0 1 0.0000 1 7 5618 47999.71 –0.0006 16.0 1 1 6 1440 48000.00 0.0000 19.2 1 1 5 1200 48000.00 0.0000 19.68 1 1 4 9951 47999.
TLV320AIC3007 SLOS619 – APRIL 2009 ..................................................................................................................................................................................................... www.ti.com STEREO AUDIO ADC HIGH PASS FILTER Often in audio applications it is desirable to remove the DC offset from the converted audio data stream. The TLV320AIC3007 has a programmable first order high pass filter which can be used for this purpose.
TLV320AIC3007 www.ti.com ..................................................................................................................................................................................................... SLOS619 – APRIL 2009 AUTOMATIC GAIN CONTROL (AGC) An automatic gain control (AGC) circuit is included with the ADC and can be used to maintain nominally constant output signal amplitude when recording speech signals (it can be fully disabled if not desired).
TLV320AIC3007 SLOS619 – APRIL 2009 ..................................................................................................................................................................................................... www.ti.com Maximum PGA gain applicable allows the user to restrict the maximum PGA gain that can be applied by the AGC algorithm. This can be used for limiting PGA gain in situations where environmental noise is greater than programmed noise threshold.
TLV320AIC3007 www.ti.com ..................................................................................................................................................................................................... SLOS619 – APRIL 2009 DIGITAL AUDIO PROCESSING FOR PLAYBACK The DAC channel consists of optional filters for de-emphasis and bass, treble, midrange level adjustment, speaker equalization, and 3-D effects processing.
TLV320AIC3007 SLOS619 – APRIL 2009 ..................................................................................................................................................................................................... www.ti.com The coefficients for this filter implement a variety of sound effects, with bass-boost or treble boost being the most commonly used in portable audio applications.
TLV320AIC3007 www.ti.com ..................................................................................................................................................................................................... SLOS619 – APRIL 2009 DIGITAL INTERPOLATION FILTER The digital interpolation filter upsamples the output of the digital audio processing block by the required oversampling ratio before data is provided to the digital delta-sigma modulator and analog reconstruction filter stages.
TLV320AIC3007 SLOS619 – APRIL 2009 ..................................................................................................................................................................................................... www.ti.com ANALOG OUTPUT COMMON-MODE ADJUSTMENT The output common-mode voltage and output range of the analog output are determined by an internal bandgap reference, in contrast to other codecs that may use a divided version of the supply.
TLV320AIC3007 www.ti.com ..................................................................................................................................................................................................... SLOS619 – APRIL 2009 AUDIO ANALOG INPUTS LINE1LP 0dB to -18dB in 0.5dB Steps LINE2LP 0dB, -6dB, or -12dB LINE1RP 0dB to -18dB in 0.5dB Steps MIC3L/LINE 1RM MIC3L 0dB to -18dB in 0.5dB Steps MIC3R MIC3R/LINE2RM Left ADC 0dB to -18dB in 0.
TLV320AIC3007 SLOS619 – APRIL 2009 ..................................................................................................................................................................................................... www.ti.com LINE1RP 0dB to -18dB in 0.5dB Steps LINE2RP/LINE2LM 0dB, -6dB, or -12dB LINE1LP 0dB to -18dB in 0.5dB Steps MIC3L/LINE 1RM MIC3L 0dB to -18dB in 0.5dB Steps MIC3R/LINE2RM MIC3R Right ADC 0dB to -18dB in 0.5dB Steps LINE1RM PDWN 0dB to -18dB in 0.
TLV320AIC3007 www.ti.com ..................................................................................................................................................................................................... SLOS619 – APRIL 2009 The TLV320AIC3007 includes seven analog audio input pins, which can be configured as up to three fully-differential pair plus one single-ended audio inputs, or up to six single-ended audio inputs. .
TLV320AIC3007 SLOS619 – APRIL 2009 ..................................................................................................................................................................................................... www.ti.com Inputs can also be selected as single-ended instead of fully-differential, and mixing or muxing into the ADC PGAs is also possible in this mode.
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TLV320AIC3007 www.ti.com ..................................................................................................................................................................................................... SLOS619 – APRIL 2009 ANALOG LINE OUTPUT DRIVERS The TLV320AIC3007 has two single-ended line output drivers, each capable of driving a 10-kΩ load. The output stage design leading to the fully differential line output drivers is shown in Figure 33 and Figure 34.
TLV320AIC3007 SLOS619 – APRIL 2009 ..................................................................................................................................................................................................... www.ti.com LINE2L 0dB to -78dB LINE2R 0dB to -78dB PGA_L 0dB to -78dB + PGA_R 0dB to -78dB DAC_L1 0dB to -78dB DAC_R1 0dB to -78dB Figure 34.
TLV320AIC3007 www.ti.com ..................................................................................................................................................................................................... SLOS619 – APRIL 2009 The output stage architecture leading to the high power output drivers is shown in Figure 35, with the volume control and mixing blocks being effectively identical to that shown in Figure 34.
TLV320AIC3007 SLOS619 – APRIL 2009 ..................................................................................................................................................................................................... www.ti.com The device includes a further option that falls between the other two – while it requires less power drawn while the output drivers are in powerdown, it also takes a slightly longer delay to power-up without artifact than if the bandgap reference is kept alive.
TLV320AIC3007 www.ti.com ..................................................................................................................................................................................................... SLOS619 – APRIL 2009 Stereo g s MICBIAS MICDET s AVDD To Detection block MIC3(L/R) Cellular g m s HPLOUT Stereo + Cellular g m s s HPROUT m = mic s = earspeaker g = ground/midbias Figure 37.
TLV320AIC3007 SLOS619 – APRIL 2009 ..................................................................................................................................................................................................... www.ti.com CLASS-D SPEAKER DRIVER Differential Class-D speaker outputs are available on the SPOP and SPOM pins as shown in Figure 39. The integrated Class-D speaker amplifier can drive a one Watt audio signal into a differential 8-Ω load.
TLV320AIC3007 www.ti.com ..................................................................................................................................................................................................... SLOS619 – APRIL 2009 GENERAL PURPOSE I/O 'AIC3107 has a dedicated pin for General Purpose IO. This pin can be used to read status of external signals through register read when configured as General Purpose Input.
TLV320AIC3007 SLOS619 – APRIL 2009 ..................................................................................................................................................................................................... www.ti.com Page 0 / Register 2: BIT Codec Sample Rate Select Register D7-D4 READ/ WRITE R/W RESET VALUE 0000 D3-D0 R/W 0000 DESCRIPTION ADC Sample Rate Select 0000: ADC Fs = Fsref/1 0001: ADC Fs = Fsref/1.5 0010: ADC Fs = Fsref/2 0011: ADC Fs = Fsref/2.
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TLV320AIC3007 SLOS619 – APRIL 2009 ..................................................................................................................................................................................................... www.ti.com Page 0 / Register 26: BIT (1) D7 READ/ WRITE R/W RESET VALUE 0 D6–D4 R/W 000 D3–D2 R/W 00 D1–D0 R/W 00 DESCRIPTION Left AGC Enable 0: Left AGC is disabled 1: Left AGC is enabled Left AGC Target Level 000: Left AGC target level = –5.
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TLV320AIC3007 SLOS619 – APRIL 2009 ..................................................................................................................................................................................................... www.ti.com Page 0 / Register 32: BIT D7–D0 READ/ WRITE R RESET VALUE 00000000 DESCRIPTION Left Channel Gain Applied by AGC Algorithm 11101000: Gain = –12.0 dB 11101001: Gain = –11.5 dB 11101010: Gain = –11.0 dB … 00000000: Gain = 0.0 dB 00000001: Gain = +0.
TLV320AIC3007 www.ti.com ..................................................................................................................................................................................................... SLOS619 – APRIL 2009 Page 0 / Register 35: BIT (1) D7–D3 READ/ WRITE R/W RESET VALUE 00000 D2–D0 R/W 000 Right AGC Noise Gate Debounce Register DESCRIPTION Right AGC Noise Detection Debounce Control These times (1) will not be accurate when double rate audio mode is enabled.
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TLV320AIC3007 www.ti.com ..................................................................................................................................................................................................... SLOS619 – APRIL 2009 Table 5. Output Stage Volume Control Settings and Gains (continued) Gain Setting Analog Gain (dB) Gain Setting Analog Gain (dB) Gain Setting Analog Gain (dB) 27 -13.5 57 -28.6 87 28 -14.0 58 -29.1 88 29 -14.5 59 -29.6 89 -44.
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TLV320AIC3007 SLOS619 – APRIL 2009 ..................................................................................................................................................................................................... www.ti.com Page 0 / Register 72: BIT D7–D 0 READ/ WRITE R RESET VALUE 00000000 Reserved. Do not write to this register.
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TLV320AIC3007 www.ti.com ..................................................................................................................................................................................................... SLOS619 – APRIL 2009 Page 0 / Register 86: BIT D7-D4 READ/ WRITE R/W RESET VALUE 0000 D3 R/W 0 D2 D1 R R 0 1 D0 R 0 DESCRIPTION LEFT_LOP Output Level Control 0000: Output level control = 0 dB 0001: Output level control = 1 dB 0010: Output level control = 2 dB ...
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TLV320AIC3007 SLOS619 – APRIL 2009 ..................................................................................................................................................................................................... www.ti.com Page 0 / Register 99: BIT D7–D0 READ/ WRITE R RESET VALUE 00000000 READ/ WRITE R RESET VALUE 00000000 DESCRIPTION Reserved. Do not write to this register.
TLV320AIC3007 www.ti.com ..................................................................................................................................................................................................... SLOS619 – APRIL 2009 Page 0 / Register 104: BIT D7 READ/ WRITE R/W RESET VALUE 0 D6-D5 R/W 00 D4-D2 R/W 000 D1-D0 R/W 00 (1) Left AGC Programmable Decay Time Register (1) DESCRIPTION Decay Time Register Selection 0: Decay time for the Left AGC is generated from Register 26.
TLV320AIC3007 SLOS619 – APRIL 2009 ..................................................................................................................................................................................................... www.ti.com Page 0 / Register 106: BIT D7 READ/ WRITE R/W RESET VALUE 0 D6-D5 R/W 00 D4-D2 R/W 000 D1-D0 R/W 00 (1) DESCRIPTION Decay Time Register Selection 0: Decay time for the Right AGC is generated from Register 29.
TLV320AIC3007 www.ti.com ..................................................................................................................................................................................................... SLOS619 – APRIL 2009 Page 0 / Register 108: BIT (1) D7 D6 READ/ WRITE R/W R/W RESET VALUE 0 0 D5 D4 R/W R/W 0 0 D3 R/W 0 D2 R/W 0 D1 R/W 0 D0 R/W 0 Passive Analog Signal Bypass Selection During Powerdown Register (1) DESCRIPTION Reserved.
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37 38 WCLK BCLK DOUT DIN MCLK 34 35 36 TLV320AIC3007IRSB Functional Block Diagram with Registers (ver. 0.96) Sample Rate Select = (R2) LINE2LP LINE2L PGA 0/+59.5dB 0.5dB steps + 1.
PACKAGE OPTION ADDENDUM www.ti.
PACKAGE MATERIALS INFORMATION www.ti.com 8-Apr-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device TLV320AIC3007IRSBT Package Package Pins Type Drawing WQFN RSB 40 SPQ 250 Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 180.0 12.4 Pack Materials-Page 1 5.3 B0 (mm) K0 (mm) P1 (mm) 5.3 1.5 8.0 W Pin1 (mm) Quadrant 12.
PACKAGE MATERIALS INFORMATION www.ti.com 8-Apr-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TLV320AIC3007IRSBT WQFN RSB 40 250 210.0 185.0 35.
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