Datasheet


SLAS412− DECEMBER 2003
www.ti.com
8
SPI TIMING DIAGRAM
t
td
t
a
t
sck
t
Lead
t
Lag
t
wsck
t
wsck
t
r
t
f
t
v
t
ho
t
dis
t
hi
t
su
SS
SCLK
MISO
MOSI
MSB OUT BIT . . . 1 LSB OUT
MSB OUT BIT . . . 1 LSB OUT
TYPICAL TIMING REQUIREMENTS
All specifications at 25°C, DVDD = 1.8 V
(1)
PARAMETER
IOVDD = 1.1 V IOVDD = 3.3 V
UNITS
PARAMETER
MIN MAX MIN MAX
UNITS
t
wsck
SCLK pulse width 27 18 ns
t
Lead
Enable lead time 18 15 ns
t
Lag
Enable lag time 18 15 ns
t
td
Sequential transfer delay 18 15 ns
t
a
Slave MISO access time 18 15 ns
t
dis
Slave MISO disable time 18 15 ns
t
su
MOSI data setup time 6 6 ns
t
hi
MOSI data hold time 6 6 ns
t
ho
MISO data hold time 4 4 ns
t
v
MISO data valid time 22 13 ns
t
r
Rise time 6 4 ns
t
f
Fall time 6 4 ns
(1)
These parameters are based on characterization and are not tested in production.