Datasheet


SLAS412− DECEMBER 2003
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18
D I
2
S MODE
In I
2
S mode, the MSB of the left channel is valid on the second rising edge of the BCLK after the falling edge of ADWS or
LRCK. Similarly the MSB of the right channel is valid on the second rising edge of the BCLK after the rising edge of
ADWS or LRCK.
BCLK
ADWS/
LRCK
DIN/
DOUT
n n−1 1 0 n n−1 1 0
LSBMSB
n
1 clock before MSB
n−2 2 n−2 2
1/fs
Left Channel Right Channel
Figure 16. Timing Diagram for I
2
S Mode
D DSP MODE
In DSP mode, the falling edge of ADWS or LRCK starts the data transfer with the left channel data first and immediately
followed by the right channel data. Each data bit is valid on the falling edge of BCLK.
BCLK
ADWS/
LRCK
DIN/
DOUT
n n−1 1 0 n n−1 1 0
LSBMSB
n n−11 0
MSB LSB
n−2 2 n−2 2 n−2
MSBLSB
1/fs
Left Channel Right Channel
Figure 17. Timing Diagram for DSP Mode