Datasheet


SLAS412− DECEMBER 2003
www.ti.com
15
OVERVIEW
The ’AIC26 is a highly integrated stereo audio codec for portable computing, communication, and entertainment
applications. The ’AIC26 has a register-based architecture where all functions are controlled through the registers and
onboard state machines.
The ’AIC26 consists of the following blocks (refer to the block diagram):
D Audio Codec
D Battery Monitors
D Auxiliary Inputs
D Temperature Monitor
Audio data is transferred between the host DSP/µP via a standard 4-wire interface and supports a variety of modes (i.e.,
I
2
S, DSP, etc).
Control of the ’AIC26 and its functions is accomplished by writing to different registers in the ’AIC26. A simple command
protocol is used to address the 16-bit registers. Registers control the operation of the A/D converter and audio codec. The
control and auxiliary functions are accessed via a SPI bus.
A typical application of the ’AIC26 is shown in Figure 13.
V1: Main Battery
V2: Secondary Battery
C1: 1 µF − 10 µF (Optional)
C2, C3, C4: 0.1 F
R1, R2: 200 − 300 
C1
Audio
R1
R2
Auxiliary Input
AUX
MICBIAS
MICIN
HPR
HPL
VGND
VBAT1
VBAT2
VREF
MCLK
ADWS/
PWDZ
DOUT
LRCK
DIN
BCLK
DAV
MISO
MOSI
SS
SCLK
8 
Speaker
C3
C4
V1 V2
C2
12S Interface
Master Clock Input
ADC Word Select
Serial Output to CPU/DSP
DAC Word Select
Serial Input From CPU/DSP
Serial Clock Input
SPI Interface
Auxiliary Data Interrupt Request to CPU
Serial Output to SPI Master
Serial Input From SPI Master
SPI Slave Select Input
SPI Serial Clock Input
2.2 k
Figure 13. Typical Circuit Configuration