Datasheet


SLAS412− DECEMBER 2003
www.ti.com
11
LRCK/ADWS
BCLK
DOUT
DIN
t
L
(BCLK)
t
s
(DI)
t
h
(DI)
t
S
(WS)
t
H
(BCLK)
t
d
(DO−BCLK)
t
h
(WS)
t
P
(BCLK)
t
h
(WS)
t
S
(WS)
Figure 4. DSP Timing in Slave Mode
TYPICAL TIMING REQUIREMENTS (FIGURE 4)
All specifications at 25°C, DVDD = 1.8 V
(1)
PARAMETER
IOVDD = 1.1 V IOVDD = 3.3 V
UNITS
PARAMETER
MIN MAX MIN MAX
UNITS
t
H
(BCLK) BCLK high period 35 35 ns
t
L
(BCLK) BCLK low period 35 35 ns
t
s
(WS) ADWS/LRCK setup 6 6 ns
t
h
(WS) ADWS/LRCK hold 6 6 ns
t
d
(DO−BCLK) BCLK to DOUT delay 25 15 ns
t
s
(DI) DIN setup 6 6 ns
t
h
(DI) DIN hold 6 6 ns
t
r
Rise time 5 4 ns
t
f
Fall time 5 4 ns
(1)
These parameters are based on characterization and are not tested in production.