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MAY 2002 Digital Audio Products

Data Manua

SLWS106D

Summary of content (46 pages)

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! " " # $#% & Data Manual MAY 2002 Digital Audio Products SLWS106D
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.
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Contents Section 1 2 3 Title Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3 Terminal Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4 Ordering Information . . . . . .
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3.3 Digital Audio Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−7 3.3.1 Digital Audio-Interface Modes . . . . . . . . . . . . . . . . . . . . . . . . 3−7 3.3.2 Audio Sampling Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−9 3.3.3 Digital Filter Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 3−11 A Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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List of Illustrations Figure Title 2−1 System-Clock Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−2 Master-Mode Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−3 Slave-Mode Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−4 Three-Wire Control Interface Timing Requirements . . . . . . . . . . . . . . . . . . . . 2−5 Two-Wire Control Interface Timing Requirements . . . . . . . . . . . . .
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vi
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1 Introduction The TLV320AIC23 is a high-performance stereo audio codec with highly integrated analog functionality. The analog-to-digital converters (ADCs) and digital-to-analog converters (DACs) within the TLV320AIC23 use multibit sigma-delta technology with integrated oversampling digital interpolation filters. Data-transfer word lengths of 16, 20, 24, and 32 bits, with sample rates from 8 kHz to 96 kHz, are supported.
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− − − • Integrated Total Electret-Microphone Biasing and Buffering Solution − − − • Low-Noise MICBIAS pin at 3/4 AVDD for Biasing of Electret Capsules Integrated Buffer Amplifier With Tunable Fixed Gain of 1 to 5 Additional Control-Register Selectable Buffer Gain of 0 dB or 20 dB Stereo-Line Inputs − − Integrated Programmable Gain Amplifier Analog Bypass Path of Codec • ADC Multiplexed Input for Stereo-Line Inputs and Microphone • Stereo-Line Outputs − Analog Stereo Mixer for DAC and Analog Bypass
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1.2 Functional Block Diagram VADC AVDD 1.0X 50 kΩ DSPcodec TLV320AIC23 VDAC VMID 1.0X VMID 50 kΩ 1.0X AGND CS Control Interface 1.5X MICBIAS SDIN SCLK MODE 12 to −34.5 dB, 1.5 dB Steps Σ−∆ ADC 2:1 MUX Line Mute RLINEIN Bypass Mute, Mute 0 dB, 20 dB 50 kΩ 10 kΩ VADC MICIN VMID 12 to −34 dB, 1.
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1.
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1.5 Terminal Functions TERMINAL NO. NAME DESCRIPTION I/O GQE PW 5 15 AVDD 4 14 BCLK 23 3 BVDD 21 1 CLKOUT 22 2 O Clock output. This is a buffered version of the XTI input and is available in 1X or 1/2X frequencies of XTI. Bit 07 in the sample rate control register controls frequency selection. CS 12 21 I DIN 24 4 I Control port input latch/address select. For SPI control mode this input acts as the data latch control.
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1−6
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2 Specifications 2.1 Absolute Maximum Ratings Over Operating Free-Air Temperature Range (unless otherwise noted)† Supply voltage range, AVDD to AGND, DVDD to DGND, BVDD to DGND, HPVDD to HPGND (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to + 3.63 V Analog supply return to digital supply return, AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to + 3 .
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2.3 Electrical Characteristics Over Recommended Operating Conditions, AVDD, HPVDD, BVDD = 3.3 V, DVDD = 1.5 V, Slave Mode, XTI/MCLK = 256fs, fs = 48 kHz (unless otherwise stated) 2.3.1 ADC 2.3.1.1 Line Input to ADC PARAMETER TEST CONDITIONS MIN Input signal level (0 dB) TYP MAX 1 fs = 48 kHz (3.3 V) fs = 48 kHz (2.7 V) Signal-to-noise ratio, A-weighted, 0-dB gain (see Notes 3 and 4) 85 90 dB 90 Dynamic range, A-weighted, −60-dB full-scale input (see Note 4) AVDD = 3.3 V AVDD = 2.
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2.3.1.3 Microphone Bias PARAMETER TEST CONDITIONS Bias voltage MIN TYP MAX 3/4 AVDD − 100 m 3/4 AVDD 3/4 AVDD + 100 m V 3 mA Bias-current source Output noise voltage 2.3.2 1 kHz to 20 kHz UNIT 25 nV/√Hz DAC 2.3.2.1 Line Output, Load = 10 kΩ, 50 pF PARAMETER TEST CONDITIONS MIN 0-dB full-scale output voltage (FFFFFF) MAX 1.0 Signal-to-noise ratio, A-weighted, 0-dB gain (see Notes 3, 4, and 5) AVDD = 3.3 V AVDD = 2.7 V Dynamic range, A-weighted (see Note 4) AVDD = 3.3 V AVDD = 2.
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2.3.4 Stereo Headphone Output PARAMETER TEST CONDITIONS MIN 0-dB full-scale output voltage TYP MAX 1.0 Maximum output power, PO RL = 32 Ω 30 RL = 16 Ω 40 Signal-to-noise ratio, A-weighted (see Note 4) AVDD = 3.3 V 90 Total harmonic distortion AVDD = 3.3 V, 1 kHz output Power supply rejection ratio 1 kHz, 100 mVpp Programmable gain 1 kHz output mW 97 dB PO = 10 mW PO = 20 mW 0.1 1.
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2.4 Digital-Interface Timing PARAMETER MIN High 18 Low 18 tw(1) tw(2) System-clock pulse duration, MCLK/XTI tc(1) System-clock period, MCLK/XTI MAX Propagation delay, CLKOUT UNIT ns 54 Duty cycle, MCLK/XTI tpd(1) TYP ns 40/60% 60/40% 0 10 ns tc(1) tw(1) tw(2) MCLK/XTI tpd(1) CLKOUT CLKOUT (Div 2) Figure 2−1. System-Clock Timing Requirements 2.4.
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2.4.2 Audio Interface (Slave-Mode) PARAMETER tw(3) tw(4) Pulse duration, BCLK MIN High 20 Low 20 TYP MAX UNIT ns tc(2) tpd(4) Clock period, BCLK 50 tsu(2) th(2) Setup time, DIN 10 ns Hold time, DIN 10 ns tsu(3) th(3) Setup time, LRCIN 10 ns Hold time, LRCIN 10 ns Propagation delay, DOUT 0 tc(2) tw(4) tw(3) BCLK LRCIN LRCOUT tsu(2) th(3) tsu(3) DIN tpd(2) th(2) DOUT Figure 2−3.
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2.4.3 Three-Wire Control Interface (SDIN) PARAMETER tw(5) tw(6) Clock pulse duration, SCLK MIN High 20 Low 20 TYP MAX UNIT ns tc(3) tsu(4) Clock period, SCLK 80 ns Clock rising edge to CS rising edge, SCLK 60 ns tsu(5) th(4) Setup time, SDIN to SCLK 20 ns Hold time, SCLK to SDIN 20 ns tw(7) tw(8) Pulse duration, CS High 20 Low 20 ns tw(8) CS tc(3) tw(5) tw(6) tsu(4) SCLK tsu(5) th(4) LSB DIN Figure 2−4. Three-Wire Control Interface Timing Requirements 2.4.
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2−8
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3 How to Use the TLV320AIC23 3.1 Control Interfaces The TLV320AIC23 has many programmable features. The control interface is used to program the registers of the device. The control interface complies with SPI (three-wire operation) and two-wire operation specifications. The state of the MODE terminal selects the control interface type. The MODE pin must be hardwired to the required level. 3.1.
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The device that recognizes the address responds by pulling SDIN low during the ninth clock cycle, acknowledging the data transfer. The control follows in the next two eight-bit blocks. The stop condition after the data transfer is a rising edge on SDIN when SCLK is high (see Figure 3-2). The 16-bit control word is divided into two parts.
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Right Line Input Channel Volume Control (Address: 0000001) BIT D8 D7 D6 D5 D4 D3 D2 D1 D0 Function RLS RIM X X RIV4 RIV3 RIV2 RIV1 RIV0 Default 0 1 0 0 1 0 1 1 1 RLS Right/left line simultaneous volume/mute update Simultaneous update 0 = Disabled 1 = Enabled Right line input mute 0 = Normal 1 = Muted Right line input volume control (10111 = 0 dB default) 11111 = +12 dB down to 00000 = –34.5 dB in 1.
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Digital Audio Path Control (Address: 0000101) BIT D8 D7 D6 D5 D4 D3 D2 D1 D0 Function X X X X X DACM DEEMP1 DEEMP0 ADCHP Default 0 0 0 0 0 0 1 0 0 DACM DEEMP[1:0] ADCHP X DAC soft mute De-emphasis control ADC high-pass filter Reserved 0 = Disabled 00 = Disabled 0 = Disabled 1 = Enabled 01 = 32 kHz 1 = Enabled 10 = 44.
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SR[3:0] BOSR Sampling rate control (see Sections 3.3.2.1 AND 3.3.2.
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The MICIN signal path has two gain stages. The first stage has a nominal gain of G1 = 50 k/10 k = 5. By adding an external resistor (RMIC) in series with MICIN, the gain of the first stage can be adjusted by G1 = 50 k/(10 k + RMIC). For example, RMIC = 40 k gives a gain of 0 dB. The second stage has a software programmable gain of 0 dB or 20 dB (see Section 3.1.3). 50 kΩ 10 kΩ MICIN To ADC VMID 0 dB/20 dB Figure 3−4. Microphone Input Circuit The microphone input is biased internally to VMID.
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3.2.5 Analog Bypass Mode The TLV320AIC23 includes a bypass mode in which the analog line inputs are directly routed to the analog line outputs, bypassing the ADC and DAC. This is enabled by selecting the bypass bit in the analog audio path control register[see Section 3.1.3). For a true bypass mode, the output from the DAC and the sidetone should be disabled. The line input and headphone output volume controls and mutes are still operational in bypass mode.
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1/fs LRCIN/ LRCOUT BCLK Left Channel DIN/ n n−1 1 Right Channel 0 n n−1 1 0 n DOUT MSB LSB Figure 3−6. Left-Justified Mode Timing 3.3.1.3 I2S Mode In I2S mode, the MSB is available on the second rising edge of BCLK, after the falling edge on LRCIN or LRCOUT (see Figure 3-7). 1/fs LRCIN/ LRCOUT BCLK 1BCLK DIN/ DOUT Left Channel n n−1 1 MSB Right Channel 0 n n−1 1 0 LSB Figure 3−7. I2S Mode Timing 3.3.1.4 DSP Mode The DSP mode is compatible with the McBSP ports of TI DSPs.
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3.3.2 Audio Sampling Rates The TLV320AIC23 can operate in master or slave clock mode. In the master mode, the TLV320AIC23 clock and sampling rates are derived from a 12-MHz MCLK signal. This 12-MHz clock signal is compatible with the USB specification. The TLV320AIC23 can be used directly in a USB system. In the slave mode, an appropriate MCLK or crystal frequency and the sample rate control register settings control the TLV320AIC23 clock and sampling rates.
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3.3.2.2 Normal-Mode Sampling Rates In normal mode, the following ADC and DAC sampling rates, depending on the MCLK frequency, are available: MCLK = 12.288 MHz SAMPLING RATE SAMPLING-RATE CONTROL SETTINGS ADC (kHz) DAC (kHz) FILTER TYPE SR3 SR2 SR1 SR0 BOSR 96 96 2 0 1 1 1 0 48 48 1 0 0 0 0 0 32 32 1 0 1 1 0 0 8 8 1 0 0 1 1 0 48 8 1 0 0 0 1 0 8 48 1 0 0 1 0 0 MCLK = 11.
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3.3.3 Digital Filter Characteristics PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ADC Filter Characteristics ( TI DSP 250 fs Mode Operation ) Passband ±0.05 dB Stopband −6 dB 0.416 fs Hz 0.5 fs Stopband attenuation Hz ±0.05 Passband ripple f > 0.584 fs −60 dB dB ADC Filter Characteristics ( TI DSP 272 fs and Normal Mode Operation ) Passband ±0.05 dB Stopband −6 dB 0.4535 fs Hz 0.5 fs Stopband attenuation Hz ±0.05 Passband ripple dB f > 0.5465 fs −60 dB −3 dB, fs = 44.
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FILTER RESPONSE vs NORMALIZED AUDIO SAMPLING FREQUENCY 0 Filter Response − dB −2 −4 −6 −8 −10 0 0.1 0.2 0.3 0.4 0.5 Normalized Audio Sampling Frequency Figure 3−9. Digital De-Emphasis Filter Response − 44.1 kHz Sampling FILTER RESPONSE vs NORMALIZED AUDIO SAMPLING FREQUENCY 0 Filter Response − dB −2 −4 −6 −8 −10 0 0.10 0.20 0.30 0.40 0.50 Normalized Audio Sampling Frequency Figure 3−10.
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FILTER RESPONSE vs NORMALIZED AUDIO SAMPLING FREQUENCY Filter Response − dB 10 −10 −30 −50 −70 −90 0 0.5 1 2 1.5 2.5 3 Normalized Audio Sampling Frequency Figure 3−11. ADC Digital Filter Response 0: USB Mode (Group Delay = 12 Output Samples) FILTER RESPONSE vs NORMALIZED AUDIO SAMPLING FREQUENCY Filter Response − dB 0.10 0.08 0.06 0.04 0.02 0 −0.02 −0.04 −0.06 −0.08 −0.10 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 Normalized Audio Sampling Frequency Figure 3−12.
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FILTER RESPONSE vs NORMALIZED AUDIO SAMPLING FREQUENCY Filter Response − dB 10 −10 −30 −50 −70 −90 0 0.5 1 1.5 2.5 2 3 Normalized Audio Sampling Frequency Figure 3−13. ADC Digital Filter Response 1: USB Mode Only FILTER RESPONSE vs NORMALIZED AUDIO SAMPLING FREQUENCY Filter Response − dB 0.10 0.08 0.06 0.04 0.02 0 −0.02 −0.04 −0.06 −0.08 −0.10 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 Normalized Audio Sampling Frequency Figure 3−14. ADC Digital Filter Ripple 1: USB Mode Only 3−14 0.
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FILTER RESPONSE vs NORMALIZED AUDIO SAMPLING FREQUENCY Filter Response − dB 10 −10 −30 −50 −70 −90 0 0.5 1 1.5 2 2.5 3 Normalized Audio Sampling Frequency Figure 3−15. ADC Digital Filter Response 2: USB mode and Normal Modes (Group Delay = 3 Output Samples) FILTER RESPONSE vs NORMALIZED AUDIO SAMPLING FREQUENCY Filter Response − dB 0.4 0.3 0.2 0.1 0 −0.1 −0.2 −0.3 −0.4 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 Normalized Audio Sampling Frequency Figure 3−16.
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FILTER RESPONSE vs NORMALIZED AUDIO SAMPLING FREQUENCY Filter Response − dB 10 −10 −30 −50 −70 −90 0 0.5 1 1.5 2 2.5 3 Normalized Audio Sampling Frequency Figure 3−17. ADC Digital Filter Response 3: USB Mode Only FILTER RESPONSE vs NORMALIZED AUDIO SAMPLING FREQUENCY Filter Response − dB 0.4 0.3 0.2 0.1 0 −0.1 −0.2 −0.3 −0.4 0 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 Normalized Audio Sampling Frequency Figure 3−18. ADC Digital Filter Ripple 3: USB Mode Only 3−16 0.45 0.
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FILTER RESPONSE vs NORMALIZED AUDIO SAMPLING FREQUENCY Filter Response − dB 10 −10 −30 −50 −70 −90 0 0.5 1 1.5 2 Normalized Audio Sampling Frequency 2.5 3 Figure 3−19. DAC Digital Filter Response 0: USB Mode FILTER RESPONSE vs NORMALIZED AUDIO SAMPLING FREQUENCY Filter Response − dB 0.10 0.08 0.06 0.04 0.02 0 −0.02 −0.04 −0.06 −0.08 −0.10 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 Normalized Audio Sampling Frequency Figure 3−20.
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FILTER RESPONSE vs NORMALIZED AUDIO SAMPLING FREQUENCY Filter Response − dB 10 −10 −30 −50 −70 −90 0 0.5 1 1.5 2 2.5 3 Normalized Audio Sampling Frequency Figure 3−21. DAC Digital Filter Response 1: USB Mode Only FILTER RESPONSE vs NORMALIZED AUDIO SAMPLING FREQUENCY Filter Response − dB 0.10 0.08 0.06 0.04 0.02 0 −0.02 −0.04 −0.06 −0.08 −0.10 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 Normalized Audio Sampling Frequency Figure 3−22. DAC Digital Filter Ripple 1: USB Mode Only 3−18 0.
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FILTER RESPONSE vs NORMALIZED AUDIO SAMPLING FREQUENCY Filter Response − dB 10 −10 −30 −50 −70 −90 0 0.5 1 1.5 2 2.5 3 Normalized Audio Sampling Frequency Figure 3−23. DAC Digital Filter Response 2: USB Mode and Normal Modes FILTER RESPONSE vs NORMALIZED AUDIO SAMPLING FREQUENCY Filter Response − dB 0.4 0.3 0.2 0.1 0 −0.1 −0.2 −0.3 −0.4 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 Normalized Audio Sampling Frequency Figure 3−24.
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FILTER RESPONSE vs NORMALIZED AUDIO SAMPLING FREQUENCY Filter Response − dB 10 −10 −30 −50 −70 −90 0 0.5 1 1.5 2 2.5 3 Normalized Audio Sampling Frequency Figure 3−25. DAC Digital Filter Response 3: USB Mode Only FILTER RESPONSE vs NORMALIZED AUDIO SAMPLING FREQUENCY Filter Response − dB 0.4 0.3 0.2 0.1 0 −0.1 −0.2 −0.3 −0.4 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 Normalized Audio Sampling Frequency Figure 3−26.
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Appendix A Mechanical Data GQE (S-PBGA-N80) PLASTIC BALL GRID ARRAY 5,10 SQ 4,90 4,00 TYP 0,50 J 0,50 H G F E D C B A 1 0,68 0,62 2 3 4 5 6 7 8 9 1,00 MAX Seating Plane 0,35 0,25 NOTES: A. B. C. D. ∅ 0,05 M 0,21 0,11 0,08 4200461/C 10/00 All linear dimensions are in millimeters. This drawing is subject to change without notice. MicroStar Junior BGA configuration Falls within JEDEC MO-225 MicroStar Junior is a trademark of Texas Instruments.
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PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14 PINS SHOWN 0,30 0,19 0,65 14 0,10 M 8 0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 7 0°−ā 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 8 14 16 20 24 28 A MAX 3,10 5,10 5,10 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9,60 DIM 4040064/F 01/97 NOTES: A. B. C. D. A−2 All linear dimensions are in millimeters. This drawing is subject to change without notice.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 11-Nov-2009 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
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PACKAGE MATERIALS INFORMATION www.ti.com 29-Jul-2009 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TLV320AIC23IPWR TSSOP PW 28 2000 330.0 16.4 6.9 10.2 1.8 12.0 16.0 Q1 TLV320AIC23PWR TSSOP PW 28 2000 330.0 16.4 6.9 10.2 1.8 12.0 16.
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PACKAGE MATERIALS INFORMATION www.ti.com 29-Jul-2009 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TLV320AIC23IPWR TSSOP PW 28 2000 346.0 346.0 33.0 TLV320AIC23PWR TSSOP PW 28 2000 346.0 346.0 33.