Datasheet

2−5
2.4 Digital-Interface Timing
PARAMETER MIN TYP MAX UNIT
t
w(1)
System-clock pulse duration, MCLK/XTI
High 18
ns
t
w(2)
System-clock pulse duration, MCLK/XTI
Low 18
ns
t
c(1)
System-clock period, MCLK/XTI 54 ns
Duty cycle, MCLK/XTI 40/60% 60/40%
t
pd(1)
Propagation delay, CLKOUT 0 10 ns
t
c(1)
t
w(1)
t
w(2)
t
pd(1)
MCLK/XTI
CLKOUT
CLKOUT
(Div 2)
Figure 2−1. System-Clock Timing Requirements
2.4.1 Audio Interface (Master Mode)
PARAMETER MIN TYP MAX UNIT
t
pd(2)
Propagation delay, LRCIN/LRCOUT 0 10 ns
t
pd(3)
Propagation delay, DOUT 0 10 ns
t
su(1)
Setup time, DIN 10 ns
t
h(1)
Hold time, DIN 10 ns
BCLK
LRCIN
DIN
t
pd(2)
t
su(1)
t
h(1)
t
pd(3)
DOUT
LRCOUT
Figure 2−2. Master-Mode Timing Requirements